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319bbe0ef5
improve the common clock support code for MPC512x - expand the CCM register set declaration with MPC5125 related registers (which reside in the previously "reserved" area) - tell the MPC5121, MPC5123, and MPC5125 SoC variants apart, and derive the availability of components and their clocks from the detected SoC (MBX, AXE, VIU, SPDIF, PATA, SATA, PCI, second FEC, second SDHC, number of PSC components, type of NAND flash controller, interpretation of the CPMF bitfield, PSC/CAN mux0 stage input clocks, output clocks on SoC pins) - add backwards compatibility (allow operation against a device tree which lacks clock related specs) for MPC5125 FECs, too telling SoC variants apart and adjusting the clock tree's generation occurs at runtime, a common generic binary supports all of the chips the MPC5125 approach to the NFC clock (one register with two counters for the high and low periods of the clock) is not implemented, as there are no users and there is no common implementation which supports this kind of clock -- the new implementation would be unused and could not get verified, so it shall wait until there is demand Signed-off-by: Gerhard Sittig <gsi@denx.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Anatolij Gustschin <agust@denx.de>
64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
/*
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* MPC5121 Prototypes and definitions
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2.
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*/
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#ifndef __ASM_POWERPC_MPC5121_H__
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#define __ASM_POWERPC_MPC5121_H__
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/* MPC512x Reset module registers */
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struct mpc512x_reset_module {
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u32 rcwlr; /* Reset Configuration Word Low Register */
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u32 rcwhr; /* Reset Configuration Word High Register */
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u32 reserved1;
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u32 reserved2;
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u32 rsr; /* Reset Status Register */
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u32 rmr; /* Reset Mode Register */
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u32 rpr; /* Reset Protection Register */
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u32 rcr; /* Reset Control Register */
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u32 rcer; /* Reset Control Enable Register */
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};
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/*
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* Clock Control Module
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*/
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struct mpc512x_ccm {
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u32 spmr; /* System PLL Mode Register */
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u32 sccr1; /* System Clock Control Register 1 */
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u32 sccr2; /* System Clock Control Register 2 */
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u32 scfr1; /* System Clock Frequency Register 1 */
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u32 scfr2; /* System Clock Frequency Register 2 */
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u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
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u32 bcr; /* Bread Crumb Register */
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u32 psc_ccr[12]; /* PSC Clock Control Registers */
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u32 spccr; /* SPDIF Clock Control Register */
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u32 cccr; /* CFM Clock Control Register */
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u32 dccr; /* DIU Clock Control Register */
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u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
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u32 out_ccr[4]; /* OUT CLK Configure Registers */
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u32 rsv0[2]; /* Reserved */
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u32 scfr3; /* System Clock Frequency Register 3 */
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u32 rsv1[3]; /* Reserved */
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u32 spll_lock_cnt; /* System PLL Lock Counter */
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u8 res[0x6c]; /* Reserved */
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};
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/*
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* LPC Module
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*/
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struct mpc512x_lpc {
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u32 cs_cfg[8]; /* CS config */
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u32 cs_ctrl; /* CS Control Register */
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u32 cs_status; /* CS Status Register */
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u32 burst_ctrl; /* CS Burst Control Register */
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u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
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u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
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u32 alt; /* Address Latch Timing Register */
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};
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int mpc512x_cs_config(unsigned int cs, u32 val);
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#endif /* __ASM_POWERPC_MPC5121_H__ */
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