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b1b6802586
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level. It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
448 lines
9.7 KiB
Plaintext
448 lines
9.7 KiB
Plaintext
/*
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* MPC8610 HPCD Device Tree Source
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*
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* Copyright 2007-2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License Version 2 as published
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* by the Free Software Foundation.
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*/
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/dts-v1/;
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/ {
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model = "MPC8610HPCD";
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compatible = "fsl,MPC8610HPCD";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8610@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>; // L1
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i-cache-size = <32768>; // L1
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>; // 512M at 0x0
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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ranges = <0 0 0xf8000000 0x08000000
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1 0 0xf0000000 0x08000000
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2 0 0xe8400000 0x00008000
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4 0 0xe8440000 0x00008000
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5 0 0xe8480000 0x00008000
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6 0 0xe84c0000 0x00008000
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3 0 0xe8000000 0x00000020>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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flash@1,0 {
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compatible = "cfi-flash";
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reg = <1 0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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flash@2,0 {
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compatible = "fsl,mpc8610-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <2 0 0x8000>;
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};
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flash@4,0 {
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compatible = "fsl,mpc8610-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <4 0 0x8000>;
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};
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flash@5,0 {
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compatible = "fsl,mpc8610-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <5 0 0x8000>;
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};
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flash@6,0 {
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compatible = "fsl,mpc8610-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <6 0 0x8000>;
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};
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board-control@3,0 {
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compatible = "fsl,fpga-pixis";
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reg = <3 0 0x20>;
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};
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};
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soc@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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compatible = "fsl,mpc8610-immr", "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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bus-frequency = <0>;
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mcm-law@0 {
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compatible = "fsl,mcm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <10>;
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};
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mcm@1000 {
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compatible = "fsl,mpc8610-mcm", "fsl,mcm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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cs4270:codec@4f {
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compatible = "cirrus,cs4270";
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reg = <0x4f>;
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/* MCLK source is a stand-alone oscillator */
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clock-frequency = <12288000>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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display@2c000 {
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compatible = "fsl,diu";
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reg = <0x2c000 100>;
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interrupts = <72 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: interrupt-controller@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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msi@41600 {
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compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8610-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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wdt@e4000 {
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compatible = "fsl,mpc8610-wdt";
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reg = <0xe4000 0x100>;
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};
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ssi@16000 {
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compatible = "fsl,mpc8610-ssi";
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cell-index = <0>;
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reg = <0x16000 0x100>;
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interrupt-parent = <&mpic>;
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interrupts = <62 2>;
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fsl,mode = "i2s-slave";
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codec-handle = <&cs4270>;
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fsl,playback-dma = <&dma00>;
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fsl,capture-dma = <&dma01>;
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fsl,fifo-depth = <8>;
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};
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ssi@16100 {
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compatible = "fsl,mpc8610-ssi";
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cell-index = <1>;
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reg = <0x16100 0x100>;
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interrupt-parent = <&mpic>;
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interrupts = <63 2>;
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fsl,fifo-depth = <8>;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
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cell-index = <0>;
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reg = <0x21300 0x4>; /* DMA general status register */
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ranges = <0x0 0x21100 0x200>;
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dma00: dma-channel@0 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,ssi-dma-channel";
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cell-index = <0>;
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reg = <0x0 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma01: dma-channel@1 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,ssi-dma-channel";
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cell-index = <1>;
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reg = <0x80 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@2 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <2>;
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reg = <0x100 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@3 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <3>;
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reg = <0x180 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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dma@c300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
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cell-index = <1>;
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reg = <0xc300 0x4>; /* DMA general status register */
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ranges = <0x0 0xc100 0x200>;
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dma-channel@0 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <0>;
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reg = <0x0 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <76 2>;
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};
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dma-channel@1 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <1>;
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reg = <0x80 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <77 2>;
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};
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dma-channel@2 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <2>;
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reg = <0x100 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <78 2>;
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};
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dma-channel@3 {
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compatible = "fsl,mpc8610-dma-channel",
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"fsl,eloplus-dma-channel";
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cell-index = <3>;
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reg = <0x180 0x80>;
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interrupt-parent = <&mpic>;
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interrupts = <79 2>;
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};
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};
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};
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pci0: pci@e0008000 {
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compatible = "fsl,mpc8610-pci";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008000 0x1000>;
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bus-range = <0 0>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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0x8800 0 0 1 &mpic 4 1
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0x8800 0 0 2 &mpic 5 1
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0x8800 0 0 3 &mpic 6 1
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0x8800 0 0 4 &mpic 7 1
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/* IDSEL 0x12 */
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0x9000 0 0 1 &mpic 5 1
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0x9000 0 0 2 &mpic 6 1
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0x9000 0 0 3 &mpic 7 1
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0x9000 0 0 4 &mpic 4 1
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>;
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};
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pci1: pcie@e000a000 {
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compatible = "fsl,mpc8641-pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe000a000 0x1000>;
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bus-range = <1 3>;
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ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&mpic>;
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interrupts = <26 2>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x1b */
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0xd800 0 0 1 &mpic 2 1
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/* IDSEL 0x1c*/
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0xe000 0 0 1 &mpic 1 1
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0xe000 0 0 2 &mpic 1 1
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0xe000 0 0 3 &mpic 1 1
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0xe000 0 0 4 &mpic 1 1
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/* IDSEL 0x1f */
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0xf800 0 0 1 &mpic 3 2
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0xf800 0 0 2 &mpic 0 1
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>;
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pcie@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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ranges = <0x02000000 0x0 0xa0000000
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0x02000000 0x0 0xa0000000
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0x0 0x10000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00100000>;
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uli1575@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <0x02000000 0x0 0xa0000000
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0x02000000 0x0 0xa0000000
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0x0 0x10000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00100000>;
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isa@1e {
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device_type = "isa";
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <0xf000 0 0 0 0>;
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ranges = <1 0 0x01000000 0 0
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0x00001000>;
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <1 0x70 2>;
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};
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};
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};
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};
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};
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pci2: pcie@e0009000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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compatible = "fsl,mpc8641-pcie";
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reg = <0xe0009000 0x00001000>;
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ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
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0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
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bus-range = <0 255>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x0000 0 0 1 &mpic 4 1
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0x0000 0 0 2 &mpic 5 1
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0x0000 0 0 3 &mpic 6 1
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0x0000 0 0 4 &mpic 7 1>;
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interrupt-parent = <&mpic>;
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interrupts = <25 2>;
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clock-frequency = <33333333>;
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};
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};
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