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fd6b9c978d
Refine the firmware load and firmware startup process. Significant changes are to ensure the SCB and IPC area are correct before starting up the firmware, and letting the CPU firmware start up the APU firmware for us. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
123 lines
5.7 KiB
C
123 lines
5.7 KiB
C
/*
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* cx18 System Control Block initialization
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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* Copyright (C) 2008 Andy Walls <awalls@radix.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA
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*/
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#include "cx18-driver.h"
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#include "cx18-io.h"
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#include "cx18-scb.h"
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void cx18_init_scb(struct cx18 *cx)
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{
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cx18_setup_page(cx, SCB_OFFSET);
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cx18_memset_io(cx, cx->scb, 0, 0x10000);
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cx18_writel(cx, IRQ_APU_TO_CPU, &cx->scb->apu2cpu_irq);
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cx18_writel(cx, IRQ_CPU_TO_APU_ACK, &cx->scb->cpu2apu_irq_ack);
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cx18_writel(cx, IRQ_HPU_TO_CPU, &cx->scb->hpu2cpu_irq);
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cx18_writel(cx, IRQ_CPU_TO_HPU_ACK, &cx->scb->cpu2hpu_irq_ack);
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cx18_writel(cx, IRQ_PPU_TO_CPU, &cx->scb->ppu2cpu_irq);
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cx18_writel(cx, IRQ_CPU_TO_PPU_ACK, &cx->scb->cpu2ppu_irq_ack);
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cx18_writel(cx, IRQ_EPU_TO_CPU, &cx->scb->epu2cpu_irq);
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cx18_writel(cx, IRQ_CPU_TO_EPU_ACK, &cx->scb->cpu2epu_irq_ack);
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cx18_writel(cx, IRQ_CPU_TO_APU, &cx->scb->cpu2apu_irq);
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cx18_writel(cx, IRQ_APU_TO_CPU_ACK, &cx->scb->apu2cpu_irq_ack);
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cx18_writel(cx, IRQ_HPU_TO_APU, &cx->scb->hpu2apu_irq);
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cx18_writel(cx, IRQ_APU_TO_HPU_ACK, &cx->scb->apu2hpu_irq_ack);
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cx18_writel(cx, IRQ_PPU_TO_APU, &cx->scb->ppu2apu_irq);
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cx18_writel(cx, IRQ_APU_TO_PPU_ACK, &cx->scb->apu2ppu_irq_ack);
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cx18_writel(cx, IRQ_EPU_TO_APU, &cx->scb->epu2apu_irq);
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cx18_writel(cx, IRQ_APU_TO_EPU_ACK, &cx->scb->apu2epu_irq_ack);
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cx18_writel(cx, IRQ_CPU_TO_HPU, &cx->scb->cpu2hpu_irq);
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cx18_writel(cx, IRQ_HPU_TO_CPU_ACK, &cx->scb->hpu2cpu_irq_ack);
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cx18_writel(cx, IRQ_APU_TO_HPU, &cx->scb->apu2hpu_irq);
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cx18_writel(cx, IRQ_HPU_TO_APU_ACK, &cx->scb->hpu2apu_irq_ack);
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cx18_writel(cx, IRQ_PPU_TO_HPU, &cx->scb->ppu2hpu_irq);
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cx18_writel(cx, IRQ_HPU_TO_PPU_ACK, &cx->scb->hpu2ppu_irq_ack);
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cx18_writel(cx, IRQ_EPU_TO_HPU, &cx->scb->epu2hpu_irq);
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cx18_writel(cx, IRQ_HPU_TO_EPU_ACK, &cx->scb->hpu2epu_irq_ack);
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cx18_writel(cx, IRQ_CPU_TO_PPU, &cx->scb->cpu2ppu_irq);
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cx18_writel(cx, IRQ_PPU_TO_CPU_ACK, &cx->scb->ppu2cpu_irq_ack);
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cx18_writel(cx, IRQ_APU_TO_PPU, &cx->scb->apu2ppu_irq);
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cx18_writel(cx, IRQ_PPU_TO_APU_ACK, &cx->scb->ppu2apu_irq_ack);
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cx18_writel(cx, IRQ_HPU_TO_PPU, &cx->scb->hpu2ppu_irq);
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cx18_writel(cx, IRQ_PPU_TO_HPU_ACK, &cx->scb->ppu2hpu_irq_ack);
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cx18_writel(cx, IRQ_EPU_TO_PPU, &cx->scb->epu2ppu_irq);
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cx18_writel(cx, IRQ_PPU_TO_EPU_ACK, &cx->scb->ppu2epu_irq_ack);
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cx18_writel(cx, IRQ_CPU_TO_EPU, &cx->scb->cpu2epu_irq);
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cx18_writel(cx, IRQ_EPU_TO_CPU_ACK, &cx->scb->epu2cpu_irq_ack);
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cx18_writel(cx, IRQ_APU_TO_EPU, &cx->scb->apu2epu_irq);
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cx18_writel(cx, IRQ_EPU_TO_APU_ACK, &cx->scb->epu2apu_irq_ack);
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cx18_writel(cx, IRQ_HPU_TO_EPU, &cx->scb->hpu2epu_irq);
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cx18_writel(cx, IRQ_EPU_TO_HPU_ACK, &cx->scb->epu2hpu_irq_ack);
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cx18_writel(cx, IRQ_PPU_TO_EPU, &cx->scb->ppu2epu_irq);
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cx18_writel(cx, IRQ_EPU_TO_PPU_ACK, &cx->scb->epu2ppu_irq_ack);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2cpu_mb),
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&cx->scb->apu2cpu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2cpu_mb),
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&cx->scb->hpu2cpu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2cpu_mb),
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&cx->scb->ppu2cpu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2cpu_mb),
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&cx->scb->epu2cpu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2apu_mb),
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&cx->scb->cpu2apu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2apu_mb),
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&cx->scb->hpu2apu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2apu_mb),
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&cx->scb->ppu2apu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2apu_mb),
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&cx->scb->epu2apu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2hpu_mb),
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&cx->scb->cpu2hpu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2hpu_mb),
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&cx->scb->apu2hpu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2hpu_mb),
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&cx->scb->ppu2hpu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2hpu_mb),
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&cx->scb->epu2hpu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2ppu_mb),
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&cx->scb->cpu2ppu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2ppu_mb),
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&cx->scb->apu2ppu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2ppu_mb),
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&cx->scb->hpu2ppu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2ppu_mb),
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&cx->scb->epu2ppu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2epu_mb),
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&cx->scb->cpu2epu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2epu_mb),
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&cx->scb->apu2epu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2epu_mb),
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&cx->scb->hpu2epu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2epu_mb),
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&cx->scb->ppu2epu_mb_offset);
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cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu_state),
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&cx->scb->ipc_offset);
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cx18_writel(cx, 1, &cx->scb->epu_state);
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}
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