Heiko Stuebner 12551f0239 clk: rockchip: fix rk3066 pll lock bit location ... The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll. The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table. Fix this by defining separate pll definitions for rk3066 with the correct locking indices. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Fixes: 2c14736c75 ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks") Tested-by: FUKAUMI Naoki <naobsd@gmail.com> Cc: stable@vger.kernel.org		2014-12-28 23:30:08 +01:00
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clk-cpu.c	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
clk-mmc-phase.c	clk: rockchip: Add support for the mmc clock phases using the framework	2014-11-28 00:44:24 +01:00
clk-pll.c	clk: rockchip: add optional sync to pll rate parameters	2014-11-25 09:57:18 +01:00
clk-rk3188.c	clk: rockchip: fix rk3066 pll lock bit location	2014-12-28 23:30:08 +01:00
clk-rk3288.c	clk: rockchip: Add support for the mmc clock phases using the framework	2014-11-28 00:44:24 +01:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	- clock phase setting capability for the rk3288 mmc clocks	2014-11-28 21:00:16 -08:00
clk.h	clk: rockchip: Add support for the mmc clock phases using the framework	2014-11-28 00:44:24 +01:00
Makefile	clk: rockchip: Add support for the mmc clock phases using the framework	2014-11-28 00:44:24 +01:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00