mirror of
https://github.com/torvalds/linux.git
synced 2024-12-30 06:41:43 +00:00
7da7c15613
On SoCs that have the calibration MSRs available, either there is no PIT, HPET or PMTIMER to calibrate against, or the PIT/HPET/PMTIMER is driven from the same clock as the TSC, so calibration is redundant and just slows down the boot. TSC rate is caculated by this formula: <maximum core-clock to bus-clock ratio> * <maximum resolved frequency> The ratio and the resolved frequency ID can be obtained from MSR. See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5 for details. Signed-off-by: Bin Gao <bin.gao@intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> Link: http://lkml.kernel.org/n/tip-rgm7xmg7k6qnjlw3ynkcjsmh@git.kernel.org
72 lines
1.5 KiB
C
72 lines
1.5 KiB
C
/*
|
|
* x86 TSC related functions
|
|
*/
|
|
#ifndef _ASM_X86_TSC_H
|
|
#define _ASM_X86_TSC_H
|
|
|
|
#include <asm/processor.h>
|
|
|
|
#define NS_SCALE 10 /* 2^10, carefully chosen */
|
|
#define US_SCALE 32 /* 2^32, arbitralrily chosen */
|
|
|
|
/*
|
|
* Standard way to access the cycle counter.
|
|
*/
|
|
typedef unsigned long long cycles_t;
|
|
|
|
extern unsigned int cpu_khz;
|
|
extern unsigned int tsc_khz;
|
|
|
|
extern void disable_TSC(void);
|
|
|
|
static inline cycles_t get_cycles(void)
|
|
{
|
|
unsigned long long ret = 0;
|
|
|
|
#ifndef CONFIG_X86_TSC
|
|
if (!cpu_has_tsc)
|
|
return 0;
|
|
#endif
|
|
rdtscll(ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static __always_inline cycles_t vget_cycles(void)
|
|
{
|
|
/*
|
|
* We only do VDSOs on TSC capable CPUs, so this shouldn't
|
|
* access boot_cpu_data (which is not VDSO-safe):
|
|
*/
|
|
#ifndef CONFIG_X86_TSC
|
|
if (!cpu_has_tsc)
|
|
return 0;
|
|
#endif
|
|
return (cycles_t)__native_read_tsc();
|
|
}
|
|
|
|
extern void tsc_init(void);
|
|
extern void mark_tsc_unstable(char *reason);
|
|
extern int unsynchronized_tsc(void);
|
|
extern int check_tsc_unstable(void);
|
|
extern int check_tsc_disabled(void);
|
|
extern unsigned long native_calibrate_tsc(void);
|
|
|
|
extern int tsc_clocksource_reliable;
|
|
|
|
/*
|
|
* Boot-time check whether the TSCs are synchronized across
|
|
* all CPUs/cores:
|
|
*/
|
|
extern void check_tsc_sync_source(int cpu);
|
|
extern void check_tsc_sync_target(void);
|
|
|
|
extern int notsc_setup(char *);
|
|
extern void tsc_save_sched_clock_state(void);
|
|
extern void tsc_restore_sched_clock_state(void);
|
|
|
|
/* MSR based TSC calibration for Intel Atom SoC platforms */
|
|
int try_msr_calibrate_tsc(unsigned long *fast_calibrate);
|
|
|
|
#endif /* _ASM_X86_TSC_H */
|