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Dove pinctrl binding now requires three different reg properties. This updates corresponding binding and example accordingly. While at it, also document reg property as required for the other MVEBU SoC pinctrl nodes. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
91 lines
4.5 KiB
Plaintext
91 lines
4.5 KiB
Plaintext
* Marvell Dove SoC pinctrl driver for mpp
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Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "marvell,dove-pinctrl"
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- clocks: (optional) phandle of pdma clock
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- reg: register specifiers of MPP, MPP4, and PMU MPP registers
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Available mpp pins/groups and functions:
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Note: brackets (x) are not part of the mpp name for marvell,function and given
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only for more detailed description in this document.
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Note: pmu* also allows for Power Management functions listed below
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name pins functions
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================================================================================
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mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
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mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
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mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
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uart1(rts), pmu*
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mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
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uart1(cts), lcd-spi(cs1), pmu*
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mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
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mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
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mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
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mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
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mpp8 8 gpio, pmu, watchdog(rstout), pmu*
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mpp9 9 gpio, pmu, pex1(clkreq), pmu*
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mpp10 10 gpio, pmu, ssp(sclk), pmu*
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mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
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sdio1(ledctrl), pex0(clkreq), pmu*
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mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
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sata(act), pmu*
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mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
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ssp(extclk), pmu*
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mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
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mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
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mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
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mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
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ac97-1(sysclko)
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mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
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mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
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mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
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ac97(sysclko)
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mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
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uart1(cts), ssp(sfrm)
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mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
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lcd-spi(mosi), uart1(cts), ssp(txd)
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mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
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lcd-spi(sck), ssp(sclk)
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mpp_camera 24-39 gpio, camera
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mpp_sdio0 40-45 gpio, sdio0
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mpp_sdio1 46-51 gpio, sdio1
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mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
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ssp/twsi
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mpp_spi0 58-61 gpio, spi0
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mpp_uart1 62-63 gpio, uart1
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mpp_nand 64-71 gpo, nand
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audio0 - i2s, ac97
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twsi - none, opt1, opt2, opt3
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Power Management functions (pmu*):
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pmu-nc Pin not driven by any PM function
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pmu-low Pin driven low (0)
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pmu-high Pin driven high (1)
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pmic(sdi) Pin is used for PMIC SDI
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cpu-pwr-down Pin is used for CPU_PWRDWN
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standby-pwr-down Pin is used for STBY_PWRDWN
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core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
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cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
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bat-fault Pin is used for BATTERY_FAULT
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ext0-wakeup Pin is used for EXT0_WU
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ext1-wakeup Pin is used for EXT0_WU
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ext2-wakeup Pin is used for EXT0_WU
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pmu-blink Pin is used for blink function
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Notes:
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* group "mpp_audio1" allows the following functions and gpio pins:
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- gpio : gpio on pins 52-57
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- i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
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- i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
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- spdifo : spdifo on pin 57, gpio on pins 52-55
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- twsi : twsi on pins 56,57, gpio on pins 52-55
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- ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
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- ssp : ssp on pins 52-55, gpio on pins 56,57
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- ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
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* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
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audio0 pins.
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* group "twsi" internally muxes twsi controller to the dedicated or option pins.
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