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2239fe59ac
This flag doesn't look to be used by any code, just set in various clk init structures and then never tested again. Remove it from these drivers as it doesn't provide any benefit. Cc: Anders Berg <anders.berg@lsi.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
608 lines
13 KiB
C
608 lines
13 KiB
C
/*
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* drivers/clk/clk-axm5516.c
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*
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* Provides clock implementations for three different types of clock devices on
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* the Axxia device: PLL clock, a clock divider and a clock mux.
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*
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* Copyright (C) 2014 LSI Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/lsi,axm5516-clks.h>
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/**
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* struct axxia_clk - Common struct to all Axxia clocks.
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* @hw: clk_hw for the common clk framework
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* @regmap: Regmap for the clock control registers
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*/
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struct axxia_clk {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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#define to_axxia_clk(_hw) container_of(_hw, struct axxia_clk, hw)
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/**
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* struct axxia_pllclk - Axxia PLL generated clock.
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* @aclk: Common struct
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* @reg: Offset into regmap for PLL control register
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*/
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struct axxia_pllclk {
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struct axxia_clk aclk;
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u32 reg;
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};
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#define to_axxia_pllclk(_aclk) container_of(_aclk, struct axxia_pllclk, aclk)
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/**
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* axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
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* parent clock rate.
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*/
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static unsigned long
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axxia_pllclk_recalc(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct axxia_clk *aclk = to_axxia_clk(hw);
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struct axxia_pllclk *pll = to_axxia_pllclk(aclk);
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unsigned long rate, fbdiv, refdiv, postdiv;
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u32 control;
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regmap_read(aclk->regmap, pll->reg, &control);
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postdiv = ((control >> 0) & 0xf) + 1;
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fbdiv = ((control >> 4) & 0xfff) + 3;
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refdiv = ((control >> 16) & 0x1f) + 1;
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rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
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return rate;
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}
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static const struct clk_ops axxia_pllclk_ops = {
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.recalc_rate = axxia_pllclk_recalc,
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};
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/**
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* struct axxia_divclk - Axxia clock divider
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* @aclk: Common struct
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* @reg: Offset into regmap for PLL control register
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* @shift: Bit position for divider value
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* @width: Number of bits in divider value
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*/
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struct axxia_divclk {
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struct axxia_clk aclk;
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u32 reg;
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u32 shift;
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u32 width;
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};
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#define to_axxia_divclk(_aclk) container_of(_aclk, struct axxia_divclk, aclk)
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/**
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* axxia_divclk_recalc_rate - Calculate clock divider output rage
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*/
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static unsigned long
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axxia_divclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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{
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struct axxia_clk *aclk = to_axxia_clk(hw);
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struct axxia_divclk *divclk = to_axxia_divclk(aclk);
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u32 ctrl, div;
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regmap_read(aclk->regmap, divclk->reg, &ctrl);
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div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1));
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return parent_rate / div;
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}
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static const struct clk_ops axxia_divclk_ops = {
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.recalc_rate = axxia_divclk_recalc_rate,
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};
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/**
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* struct axxia_clkmux - Axxia clock mux
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* @aclk: Common struct
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* @reg: Offset into regmap for PLL control register
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* @shift: Bit position for selection value
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* @width: Number of bits in selection value
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*/
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struct axxia_clkmux {
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struct axxia_clk aclk;
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u32 reg;
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u32 shift;
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u32 width;
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};
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#define to_axxia_clkmux(_aclk) container_of(_aclk, struct axxia_clkmux, aclk)
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/**
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* axxia_clkmux_get_parent - Return the index of selected parent clock
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*/
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static u8 axxia_clkmux_get_parent(struct clk_hw *hw)
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{
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struct axxia_clk *aclk = to_axxia_clk(hw);
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struct axxia_clkmux *mux = to_axxia_clkmux(aclk);
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u32 ctrl, parent;
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regmap_read(aclk->regmap, mux->reg, &ctrl);
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parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1);
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return (u8) parent;
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}
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static const struct clk_ops axxia_clkmux_ops = {
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.get_parent = axxia_clkmux_get_parent,
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};
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/*
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* PLLs
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*/
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static struct axxia_pllclk clk_fab_pll = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_fab_pll",
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.parent_names = (const char *[]){
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"clk_ref0"
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},
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.num_parents = 1,
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.ops = &axxia_pllclk_ops,
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},
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.reg = 0x01800,
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};
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static struct axxia_pllclk clk_cpu_pll = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu_pll",
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.parent_names = (const char *[]){
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"clk_ref0"
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},
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.num_parents = 1,
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.ops = &axxia_pllclk_ops,
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},
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.reg = 0x02000,
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};
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static struct axxia_pllclk clk_sys_pll = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_sys_pll",
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.parent_names = (const char *[]){
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"clk_ref0"
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},
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.num_parents = 1,
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.ops = &axxia_pllclk_ops,
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},
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.reg = 0x02800,
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};
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static struct axxia_pllclk clk_sm0_pll = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_sm0_pll",
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.parent_names = (const char *[]){
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"clk_ref2"
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},
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.num_parents = 1,
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.ops = &axxia_pllclk_ops,
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},
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.reg = 0x03000,
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};
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static struct axxia_pllclk clk_sm1_pll = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_sm1_pll",
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.parent_names = (const char *[]){
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"clk_ref1"
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},
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.num_parents = 1,
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.ops = &axxia_pllclk_ops,
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},
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.reg = 0x03800,
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};
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/*
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* Clock dividers
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*/
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static struct axxia_divclk clk_cpu0_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu0_div",
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.parent_names = (const char *[]){
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"clk_cpu_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x10008,
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.shift = 0,
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.width = 4,
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};
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static struct axxia_divclk clk_cpu1_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu1_div",
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.parent_names = (const char *[]){
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"clk_cpu_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x10008,
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.shift = 4,
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.width = 4,
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};
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static struct axxia_divclk clk_cpu2_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu2_div",
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.parent_names = (const char *[]){
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"clk_cpu_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x10008,
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.shift = 8,
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.width = 4,
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};
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static struct axxia_divclk clk_cpu3_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu3_div",
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.parent_names = (const char *[]){
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"clk_cpu_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x10008,
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.shift = 12,
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.width = 4,
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};
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static struct axxia_divclk clk_nrcp_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_nrcp_div",
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.parent_names = (const char *[]){
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"clk_sys_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x1000c,
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.shift = 0,
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.width = 4,
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};
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static struct axxia_divclk clk_sys_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_sys_div",
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.parent_names = (const char *[]){
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"clk_sys_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x1000c,
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.shift = 4,
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.width = 4,
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};
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static struct axxia_divclk clk_fab_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_fab_div",
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.parent_names = (const char *[]){
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"clk_fab_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x1000c,
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.shift = 8,
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.width = 4,
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};
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static struct axxia_divclk clk_per_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_per_div",
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.parent_names = (const char *[]){
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"clk_sm1_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x1000c,
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.shift = 12,
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.width = 4,
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};
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static struct axxia_divclk clk_mmc_div = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_mmc_div",
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.parent_names = (const char *[]){
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"clk_sm1_pll"
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},
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.num_parents = 1,
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.ops = &axxia_divclk_ops,
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},
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.reg = 0x1000c,
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.shift = 16,
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.width = 4,
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};
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/*
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* Clock MUXes
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*/
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static struct axxia_clkmux clk_cpu0_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu0",
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.parent_names = (const char *[]){
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"clk_ref0",
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"clk_cpu_pll",
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"clk_cpu0_div",
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"clk_cpu0_div"
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},
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.num_parents = 4,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10000,
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.shift = 0,
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.width = 2,
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};
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static struct axxia_clkmux clk_cpu1_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu1",
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.parent_names = (const char *[]){
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"clk_ref0",
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"clk_cpu_pll",
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"clk_cpu1_div",
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"clk_cpu1_div"
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},
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.num_parents = 4,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10000,
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.shift = 2,
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.width = 2,
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};
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static struct axxia_clkmux clk_cpu2_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu2",
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.parent_names = (const char *[]){
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"clk_ref0",
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"clk_cpu_pll",
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"clk_cpu2_div",
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"clk_cpu2_div"
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},
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.num_parents = 4,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10000,
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.shift = 4,
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.width = 2,
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};
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static struct axxia_clkmux clk_cpu3_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_cpu3",
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.parent_names = (const char *[]){
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"clk_ref0",
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"clk_cpu_pll",
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"clk_cpu3_div",
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"clk_cpu3_div"
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},
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.num_parents = 4,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10000,
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.shift = 6,
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.width = 2,
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};
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static struct axxia_clkmux clk_nrcp_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_nrcp",
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.parent_names = (const char *[]){
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"clk_ref0",
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"clk_sys_pll",
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"clk_nrcp_div",
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"clk_nrcp_div"
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},
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.num_parents = 4,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10004,
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.shift = 0,
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.width = 2,
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};
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static struct axxia_clkmux clk_sys_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_sys",
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.parent_names = (const char *[]){
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"clk_ref0",
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"clk_sys_pll",
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"clk_sys_div",
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"clk_sys_div"
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},
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.num_parents = 4,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10004,
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.shift = 2,
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.width = 2,
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};
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static struct axxia_clkmux clk_fab_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_fab",
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.parent_names = (const char *[]){
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"clk_ref0",
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"clk_fab_pll",
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"clk_fab_div",
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"clk_fab_div"
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},
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.num_parents = 4,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10004,
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.shift = 4,
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.width = 2,
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};
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static struct axxia_clkmux clk_per_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_per",
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.parent_names = (const char *[]){
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"clk_ref1",
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"clk_per_div"
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},
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.num_parents = 2,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10004,
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.shift = 6,
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.width = 1,
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};
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static struct axxia_clkmux clk_mmc_mux = {
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.aclk.hw.init = &(struct clk_init_data){
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.name = "clk_mmc",
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.parent_names = (const char *[]){
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"clk_ref1",
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"clk_mmc_div"
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},
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.num_parents = 2,
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.ops = &axxia_clkmux_ops,
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},
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.reg = 0x10004,
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.shift = 9,
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.width = 1,
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};
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/* Table of all supported clocks indexed by the clock identifiers from the
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* device tree binding
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*/
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static struct axxia_clk *axmclk_clocks[] = {
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[AXXIA_CLK_FAB_PLL] = &clk_fab_pll.aclk,
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[AXXIA_CLK_CPU_PLL] = &clk_cpu_pll.aclk,
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[AXXIA_CLK_SYS_PLL] = &clk_sys_pll.aclk,
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[AXXIA_CLK_SM0_PLL] = &clk_sm0_pll.aclk,
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[AXXIA_CLK_SM1_PLL] = &clk_sm1_pll.aclk,
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[AXXIA_CLK_FAB_DIV] = &clk_fab_div.aclk,
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[AXXIA_CLK_SYS_DIV] = &clk_sys_div.aclk,
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[AXXIA_CLK_NRCP_DIV] = &clk_nrcp_div.aclk,
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[AXXIA_CLK_CPU0_DIV] = &clk_cpu0_div.aclk,
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[AXXIA_CLK_CPU1_DIV] = &clk_cpu1_div.aclk,
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[AXXIA_CLK_CPU2_DIV] = &clk_cpu2_div.aclk,
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[AXXIA_CLK_CPU3_DIV] = &clk_cpu3_div.aclk,
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[AXXIA_CLK_PER_DIV] = &clk_per_div.aclk,
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[AXXIA_CLK_MMC_DIV] = &clk_mmc_div.aclk,
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[AXXIA_CLK_FAB] = &clk_fab_mux.aclk,
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[AXXIA_CLK_SYS] = &clk_sys_mux.aclk,
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[AXXIA_CLK_NRCP] = &clk_nrcp_mux.aclk,
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[AXXIA_CLK_CPU0] = &clk_cpu0_mux.aclk,
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[AXXIA_CLK_CPU1] = &clk_cpu1_mux.aclk,
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[AXXIA_CLK_CPU2] = &clk_cpu2_mux.aclk,
|
|
[AXXIA_CLK_CPU3] = &clk_cpu3_mux.aclk,
|
|
[AXXIA_CLK_PER] = &clk_per_mux.aclk,
|
|
[AXXIA_CLK_MMC] = &clk_mmc_mux.aclk,
|
|
};
|
|
|
|
static struct clk_hw *
|
|
of_clk_axmclk_get(struct of_phandle_args *clkspec, void *unused)
|
|
{
|
|
unsigned int idx = clkspec->args[0];
|
|
|
|
if (idx >= ARRAY_SIZE(axmclk_clocks)) {
|
|
pr_err("%s: invalid index %u\n", __func__, idx);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
return &axmclk_clocks[idx]->hw;
|
|
}
|
|
|
|
static const struct regmap_config axmclk_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x1fffc,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct of_device_id axmclk_match_table[] = {
|
|
{ .compatible = "lsi,axm5516-clks" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, axmclk_match_table);
|
|
|
|
static int axmclk_probe(struct platform_device *pdev)
|
|
{
|
|
void __iomem *base;
|
|
struct resource *res;
|
|
int i, ret;
|
|
struct device *dev = &pdev->dev;
|
|
struct regmap *regmap;
|
|
size_t num_clks;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
regmap = devm_regmap_init_mmio(dev, base, &axmclk_regmap_config);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
num_clks = ARRAY_SIZE(axmclk_clocks);
|
|
pr_info("axmclk: supporting %zu clocks\n", num_clks);
|
|
|
|
/* Update each entry with the allocated regmap and register the clock
|
|
* with the common clock framework
|
|
*/
|
|
for (i = 0; i < num_clks; i++) {
|
|
axmclk_clocks[i]->regmap = regmap;
|
|
ret = devm_clk_hw_register(dev, &axmclk_clocks[i]->hw);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return of_clk_add_hw_provider(dev->of_node, of_clk_axmclk_get, NULL);
|
|
}
|
|
|
|
static int axmclk_remove(struct platform_device *pdev)
|
|
{
|
|
of_clk_del_provider(pdev->dev.of_node);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver axmclk_driver = {
|
|
.probe = axmclk_probe,
|
|
.remove = axmclk_remove,
|
|
.driver = {
|
|
.name = "clk-axm5516",
|
|
.of_match_table = axmclk_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init axmclk_init(void)
|
|
{
|
|
return platform_driver_register(&axmclk_driver);
|
|
}
|
|
core_initcall(axmclk_init);
|
|
|
|
static void __exit axmclk_exit(void)
|
|
{
|
|
platform_driver_unregister(&axmclk_driver);
|
|
}
|
|
module_exit(axmclk_exit);
|
|
|
|
MODULE_DESCRIPTION("AXM5516 clock driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:clk-axm5516");
|