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578bffc82e
Commitfbde2d7d82
("MIPS: Add generic SMP IPI support") introduced code that BUG_ON's in the case of a kernel that supports IPI domains but does not have one at runtime. This case is possible on Malta where for IPIs we may use either the GIC (which has an IPI IRQ domain implementation) or core-local software interrupts between VPEs (which do not currently have an IPI IRQ domain implementation). We can not know which will be used until runtime when we know whether a GIC is actually present, and if we run on a system with multiple VPEs and no GIC then the BUG_ON is hit. Commit19fb5818ed
("IPS: Fix broken malta qemu") worked around this for the single-core single-VPE case typically seen using QEMU, but does not catch the multi-VPE case. This patch removes the insufficient CPU presence check that was added and works around the bug differently, effectively reverting that commit. A simple way to reproduce this bug is by using QEMU, which partially implements the MT ASE but does not implement the GIC as of version 2.5. Using "-cpu 34Kf -smp 2" will present a system with 2 VPEs in one core & no GIC, hitting the BUG_ON. Given that we're post-merge-window on the way to v4.6, avoid this by just returning from mips_smp_ipi_init when no IPI IRQ domain is found. Ideally at some point all IPI implementations would be converted to the same IPI IRQ domain interface & we'd be able to restore the check. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Fixes:fbde2d7d82
("MIPS: Add generic SMP IPI support") Fixes:19fb5818ed
("IPS: Fix broken malta qemu") Reverts:19fb5818ed
("IPS: Fix broken malta qemu") Cc: Qais Yousef <qsyousef@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
645 lines
15 KiB
C
645 lines
15 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2000, 2001 Kanoj Sarcar
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* Copyright (C) 2000, 2001 Ralf Baechle
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* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2000, 2001, 2003 Broadcom Corporation
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*/
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#include <linux/cache.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/threads.h>
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#include <linux/module.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/ftrace.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/atomic.h>
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#include <asm/cpu.h>
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#include <asm/processor.h>
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#include <asm/idle.h>
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#include <asm/r4k-timer.h>
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#include <asm/mips-cpc.h>
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#include <asm/mmu_context.h>
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#include <asm/time.h>
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#include <asm/setup.h>
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#include <asm/maar.h>
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cpumask_t cpu_callin_map; /* Bitmask of started secondaries */
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int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
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EXPORT_SYMBOL(__cpu_number_map);
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int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
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EXPORT_SYMBOL(__cpu_logical_map);
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/* Number of TCs (or siblings in Intel speak) per CPU core */
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int smp_num_siblings = 1;
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EXPORT_SYMBOL(smp_num_siblings);
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/* representing the TCs (or siblings in Intel speak) of each logical CPU */
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cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_sibling_map);
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/* representing the core map of multi-core chips of each logical CPU */
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cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_core_map);
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/*
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* A logcal cpu mask containing only one VPE per core to
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* reduce the number of IPIs on large MT systems.
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*/
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cpumask_t cpu_foreign_map __read_mostly;
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EXPORT_SYMBOL(cpu_foreign_map);
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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/* representing cpus for which core maps can be computed */
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static cpumask_t cpu_core_setup_map;
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cpumask_t cpu_coherent_mask;
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#ifdef CONFIG_GENERIC_IRQ_IPI
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static struct irq_desc *call_desc;
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static struct irq_desc *sched_desc;
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#endif
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static inline void set_cpu_sibling_map(int cpu)
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{
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int i;
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cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
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if (smp_num_siblings > 1) {
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for_each_cpu(i, &cpu_sibling_setup_map) {
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if (cpu_data[cpu].package == cpu_data[i].package &&
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cpu_data[cpu].core == cpu_data[i].core) {
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cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
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cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
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}
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}
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} else
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cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
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}
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static inline void set_cpu_core_map(int cpu)
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{
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int i;
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cpumask_set_cpu(cpu, &cpu_core_setup_map);
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for_each_cpu(i, &cpu_core_setup_map) {
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if (cpu_data[cpu].package == cpu_data[i].package) {
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cpumask_set_cpu(i, &cpu_core_map[cpu]);
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cpumask_set_cpu(cpu, &cpu_core_map[i]);
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}
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}
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}
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/*
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* Calculate a new cpu_foreign_map mask whenever a
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* new cpu appears or disappears.
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*/
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static inline void calculate_cpu_foreign_map(void)
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{
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int i, k, core_present;
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cpumask_t temp_foreign_map;
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/* Re-calculate the mask */
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cpumask_clear(&temp_foreign_map);
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for_each_online_cpu(i) {
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core_present = 0;
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for_each_cpu(k, &temp_foreign_map)
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if (cpu_data[i].package == cpu_data[k].package &&
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cpu_data[i].core == cpu_data[k].core)
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core_present = 1;
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if (!core_present)
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cpumask_set_cpu(i, &temp_foreign_map);
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}
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cpumask_copy(&cpu_foreign_map, &temp_foreign_map);
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}
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struct plat_smp_ops *mp_ops;
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EXPORT_SYMBOL(mp_ops);
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void register_smp_ops(struct plat_smp_ops *ops)
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{
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if (mp_ops)
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printk(KERN_WARNING "Overriding previously set SMP ops\n");
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mp_ops = ops;
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}
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#ifdef CONFIG_GENERIC_IRQ_IPI
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void mips_smp_send_ipi_single(int cpu, unsigned int action)
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{
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mips_smp_send_ipi_mask(cpumask_of(cpu), action);
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}
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void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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{
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unsigned long flags;
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unsigned int core;
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int cpu;
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local_irq_save(flags);
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switch (action) {
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case SMP_CALL_FUNCTION:
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__ipi_send_mask(call_desc, mask);
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break;
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case SMP_RESCHEDULE_YOURSELF:
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__ipi_send_mask(sched_desc, mask);
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break;
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default:
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BUG();
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}
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if (mips_cpc_present()) {
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for_each_cpu(cpu, mask) {
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core = cpu_data[cpu].core;
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if (core == current_cpu_data.core)
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continue;
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while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
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mips_cpc_lock_other(core);
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write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
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mips_cpc_unlock_other();
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}
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}
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}
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local_irq_restore(flags);
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}
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static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
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{
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scheduler_ipi();
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return IRQ_HANDLED;
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}
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static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
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{
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generic_smp_call_function_interrupt();
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return IRQ_HANDLED;
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}
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static struct irqaction irq_resched = {
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.handler = ipi_resched_interrupt,
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.flags = IRQF_PERCPU,
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.name = "IPI resched"
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};
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static struct irqaction irq_call = {
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.handler = ipi_call_interrupt,
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.flags = IRQF_PERCPU,
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.name = "IPI call"
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};
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static __init void smp_ipi_init_one(unsigned int virq,
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struct irqaction *action)
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{
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int ret;
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irq_set_handler(virq, handle_percpu_irq);
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ret = setup_irq(virq, action);
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BUG_ON(ret);
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}
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static int __init mips_smp_ipi_init(void)
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{
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unsigned int call_virq, sched_virq;
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struct irq_domain *ipidomain;
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struct device_node *node;
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node = of_irq_find_parent(of_root);
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ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
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/*
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* Some platforms have half DT setup. So if we found irq node but
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* didn't find an ipidomain, try to search for one that is not in the
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* DT.
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*/
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if (node && !ipidomain)
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ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI);
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/*
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* There are systems which only use IPI domains some of the time,
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* depending upon configuration we don't know until runtime. An
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* example is Malta where we may compile in support for GIC & the
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* MT ASE, but run on a system which has multiple VPEs in a single
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* core and doesn't include a GIC. Until all IPI implementations
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* have been converted to use IPI domains the best we can do here
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* is to return & hope some other code sets up the IPIs.
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*/
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if (!ipidomain)
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return 0;
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call_virq = irq_reserve_ipi(ipidomain, cpu_possible_mask);
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BUG_ON(!call_virq);
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sched_virq = irq_reserve_ipi(ipidomain, cpu_possible_mask);
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BUG_ON(!sched_virq);
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if (irq_domain_is_ipi_per_cpu(ipidomain)) {
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int cpu;
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for_each_cpu(cpu, cpu_possible_mask) {
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smp_ipi_init_one(call_virq + cpu, &irq_call);
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smp_ipi_init_one(sched_virq + cpu, &irq_resched);
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}
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} else {
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smp_ipi_init_one(call_virq, &irq_call);
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smp_ipi_init_one(sched_virq, &irq_resched);
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}
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call_desc = irq_to_desc(call_virq);
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sched_desc = irq_to_desc(sched_virq);
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return 0;
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}
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early_initcall(mips_smp_ipi_init);
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#endif
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/*
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* First C code run on the secondary CPUs after being started up by
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* the master.
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*/
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asmlinkage void start_secondary(void)
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{
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unsigned int cpu;
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cpu_probe();
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per_cpu_trap_init(false);
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mips_clockevent_init();
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mp_ops->init_secondary();
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cpu_report();
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maar_init();
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/*
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* XXX parity protection should be folded in here when it's converted
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* to an option instead of something based on .cputype
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*/
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calibrate_delay();
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preempt_disable();
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cpu = smp_processor_id();
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cpu_data[cpu].udelay_val = loops_per_jiffy;
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cpumask_set_cpu(cpu, &cpu_coherent_mask);
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notify_cpu_starting(cpu);
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set_cpu_online(cpu, true);
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set_cpu_sibling_map(cpu);
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set_cpu_core_map(cpu);
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calculate_cpu_foreign_map();
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cpumask_set_cpu(cpu, &cpu_callin_map);
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synchronise_count_slave(cpu);
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/*
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* irq will be enabled in ->smp_finish(), enabling it too early
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* is dangerous.
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*/
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WARN_ON_ONCE(!irqs_disabled());
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mp_ops->smp_finish();
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cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
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}
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static void stop_this_cpu(void *dummy)
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{
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/*
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* Remove this CPU. Be a bit slow here and
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* set the bits for every online CPU so we don't miss
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* any IPI whilst taking this VPE down.
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*/
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cpumask_copy(&cpu_foreign_map, cpu_online_mask);
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/* Make it visible to every other CPU */
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smp_mb();
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set_cpu_online(smp_processor_id(), false);
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calculate_cpu_foreign_map();
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local_irq_disable();
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while (1);
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}
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void smp_send_stop(void)
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{
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smp_call_function(stop_this_cpu, NULL, 0);
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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}
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/* called from main before smp_init() */
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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init_new_context(current, &init_mm);
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current_thread_info()->cpu = 0;
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mp_ops->prepare_cpus(max_cpus);
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set_cpu_sibling_map(0);
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set_cpu_core_map(0);
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calculate_cpu_foreign_map();
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#ifndef CONFIG_HOTPLUG_CPU
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init_cpu_present(cpu_possible_mask);
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#endif
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cpumask_copy(&cpu_coherent_mask, cpu_possible_mask);
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}
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/* preload SMP state for boot cpu */
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void smp_prepare_boot_cpu(void)
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{
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set_cpu_possible(0, true);
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set_cpu_online(0, true);
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cpumask_set_cpu(0, &cpu_callin_map);
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}
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int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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mp_ops->boot_secondary(cpu, tidle);
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/*
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* Trust is futile. We should really have timeouts ...
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*/
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while (!cpumask_test_cpu(cpu, &cpu_callin_map)) {
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udelay(100);
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schedule();
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}
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synchronise_count_master(cpu);
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return 0;
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}
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/* Not really SMP stuff ... */
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int setup_profiling_timer(unsigned int multiplier)
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{
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return 0;
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}
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static void flush_tlb_all_ipi(void *info)
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{
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local_flush_tlb_all();
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(flush_tlb_all_ipi, NULL, 1);
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}
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static void flush_tlb_mm_ipi(void *mm)
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{
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local_flush_tlb_mm((struct mm_struct *)mm);
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}
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/*
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* Special Variant of smp_call_function for use by TLB functions:
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*
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* o No return value
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* o collapses to normal function call on UP kernels
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* o collapses to normal function call on systems with a single shared
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* primary cache.
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*/
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static inline void smp_on_other_tlbs(void (*func) (void *info), void *info)
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{
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smp_call_function(func, info, 1);
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}
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static inline void smp_on_each_tlb(void (*func) (void *info), void *info)
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{
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preempt_disable();
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smp_on_other_tlbs(func, info);
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func(info);
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preempt_enable();
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}
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/*
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* The following tlb flush calls are invoked when old translations are
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* being torn down, or pte attributes are changing. For single threaded
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* address spaces, a new context is obtained on the current cpu, and tlb
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* context on other cpus are invalidated to force a new context allocation
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* at switch_mm time, should the mm ever be used on other cpus. For
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* multithreaded address spaces, intercpu interrupts have to be sent.
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* Another case where intercpu interrupts are required is when the target
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* mm might be active on another cpu (eg debuggers doing the flushes on
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* behalf of debugees, kswapd stealing pages from another process etc).
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* Kanoj 07/00.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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preempt_disable();
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if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
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smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
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} else {
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unsigned int cpu;
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for_each_online_cpu(cpu) {
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if (cpu != smp_processor_id() && cpu_context(cpu, mm))
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cpu_context(cpu, mm) = 0;
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}
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}
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local_flush_tlb_mm(mm);
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preempt_enable();
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}
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struct flush_tlb_data {
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struct vm_area_struct *vma;
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unsigned long addr1;
|
|
unsigned long addr2;
|
|
};
|
|
|
|
static void flush_tlb_range_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
|
|
}
|
|
|
|
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
|
|
{
|
|
struct mm_struct *mm = vma->vm_mm;
|
|
|
|
preempt_disable();
|
|
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
|
|
struct flush_tlb_data fd = {
|
|
.vma = vma,
|
|
.addr1 = start,
|
|
.addr2 = end,
|
|
};
|
|
|
|
smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
|
|
} else {
|
|
unsigned int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu != smp_processor_id() && cpu_context(cpu, mm))
|
|
cpu_context(cpu, mm) = 0;
|
|
}
|
|
}
|
|
local_flush_tlb_range(vma, start, end);
|
|
preempt_enable();
|
|
}
|
|
|
|
static void flush_tlb_kernel_range_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
|
|
}
|
|
|
|
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
|
|
{
|
|
struct flush_tlb_data fd = {
|
|
.addr1 = start,
|
|
.addr2 = end,
|
|
};
|
|
|
|
on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
|
|
}
|
|
|
|
static void flush_tlb_page_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_page(fd->vma, fd->addr1);
|
|
}
|
|
|
|
void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
|
|
{
|
|
preempt_disable();
|
|
if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
|
|
struct flush_tlb_data fd = {
|
|
.vma = vma,
|
|
.addr1 = page,
|
|
};
|
|
|
|
smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
|
|
} else {
|
|
unsigned int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
|
|
cpu_context(cpu, vma->vm_mm) = 0;
|
|
}
|
|
}
|
|
local_flush_tlb_page(vma, page);
|
|
preempt_enable();
|
|
}
|
|
|
|
static void flush_tlb_one_ipi(void *info)
|
|
{
|
|
unsigned long vaddr = (unsigned long) info;
|
|
|
|
local_flush_tlb_one(vaddr);
|
|
}
|
|
|
|
void flush_tlb_one(unsigned long vaddr)
|
|
{
|
|
smp_on_each_tlb(flush_tlb_one_ipi, (void *) vaddr);
|
|
}
|
|
|
|
EXPORT_SYMBOL(flush_tlb_page);
|
|
EXPORT_SYMBOL(flush_tlb_one);
|
|
|
|
#if defined(CONFIG_KEXEC)
|
|
void (*dump_ipi_function_ptr)(void *) = NULL;
|
|
void dump_send_ipi(void (*dump_ipi_callback)(void *))
|
|
{
|
|
int i;
|
|
int cpu = smp_processor_id();
|
|
|
|
dump_ipi_function_ptr = dump_ipi_callback;
|
|
smp_mb();
|
|
for_each_online_cpu(i)
|
|
if (i != cpu)
|
|
mp_ops->send_ipi_single(i, SMP_DUMP);
|
|
|
|
}
|
|
EXPORT_SYMBOL(dump_send_ipi);
|
|
#endif
|
|
|
|
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
|
|
|
static DEFINE_PER_CPU(atomic_t, tick_broadcast_count);
|
|
static DEFINE_PER_CPU(struct call_single_data, tick_broadcast_csd);
|
|
|
|
void tick_broadcast(const struct cpumask *mask)
|
|
{
|
|
atomic_t *count;
|
|
struct call_single_data *csd;
|
|
int cpu;
|
|
|
|
for_each_cpu(cpu, mask) {
|
|
count = &per_cpu(tick_broadcast_count, cpu);
|
|
csd = &per_cpu(tick_broadcast_csd, cpu);
|
|
|
|
if (atomic_inc_return(count) == 1)
|
|
smp_call_function_single_async(cpu, csd);
|
|
}
|
|
}
|
|
|
|
static void tick_broadcast_callee(void *info)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
tick_receive_broadcast();
|
|
atomic_set(&per_cpu(tick_broadcast_count, cpu), 0);
|
|
}
|
|
|
|
static int __init tick_broadcast_init(void)
|
|
{
|
|
struct call_single_data *csd;
|
|
int cpu;
|
|
|
|
for (cpu = 0; cpu < NR_CPUS; cpu++) {
|
|
csd = &per_cpu(tick_broadcast_csd, cpu);
|
|
csd->func = tick_broadcast_callee;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(tick_broadcast_init);
|
|
|
|
#endif /* CONFIG_GENERIC_CLOCKEVENTS_BROADCAST */
|