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b48d6aab37
Tegra30 has more powerdomains than Tegra20. The debugfs code did not take this into account. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
280 lines
5.7 KiB
C
280 lines
5.7 KiB
C
/*
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* drivers/powergate/tegra-powergate.c
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*
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* Copyright (c) 2010 Google, Inc
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/seq_file.h>
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#include <linux/spinlock.h>
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#include <mach/clk.h>
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#include <mach/iomap.h>
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#include <mach/powergate.h>
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#include "fuse.h"
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#define PWRGATE_TOGGLE 0x30
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#define PWRGATE_TOGGLE_START (1 << 8)
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#define REMOVE_CLAMPING 0x34
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#define PWRGATE_STATUS 0x38
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static int tegra_num_powerdomains;
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static int tegra_num_cpu_domains;
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static u8 *tegra_cpu_domains;
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static u8 tegra30_cpu_domains[] = {
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TEGRA_POWERGATE_CPU0,
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TEGRA_POWERGATE_CPU1,
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TEGRA_POWERGATE_CPU2,
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TEGRA_POWERGATE_CPU3,
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};
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static DEFINE_SPINLOCK(tegra_powergate_lock);
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static u32 pmc_read(unsigned long reg)
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{
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return readl(pmc + reg);
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}
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static void pmc_write(u32 val, unsigned long reg)
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{
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writel(val, pmc + reg);
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}
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static int tegra_powergate_set(int id, bool new_state)
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{
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bool status;
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unsigned long flags;
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spin_lock_irqsave(&tegra_powergate_lock, flags);
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status = pmc_read(PWRGATE_STATUS) & (1 << id);
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if (status == new_state) {
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spin_unlock_irqrestore(&tegra_powergate_lock, flags);
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return -EINVAL;
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}
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pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
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spin_unlock_irqrestore(&tegra_powergate_lock, flags);
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return 0;
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}
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int tegra_powergate_power_on(int id)
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{
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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return tegra_powergate_set(id, true);
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}
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int tegra_powergate_power_off(int id)
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{
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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return tegra_powergate_set(id, false);
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}
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int tegra_powergate_is_powered(int id)
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{
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u32 status;
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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status = pmc_read(PWRGATE_STATUS) & (1 << id);
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return !!status;
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}
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int tegra_powergate_remove_clamping(int id)
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{
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u32 mask;
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if (id < 0 || id >= tegra_num_powerdomains)
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return -EINVAL;
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/*
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* Tegra 2 has a bug where PCIE and VDE clamping masks are
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* swapped relatively to the partition ids
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*/
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if (id == TEGRA_POWERGATE_VDEC)
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mask = (1 << TEGRA_POWERGATE_PCIE);
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else if (id == TEGRA_POWERGATE_PCIE)
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mask = (1 << TEGRA_POWERGATE_VDEC);
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else
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mask = (1 << id);
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pmc_write(mask, REMOVE_CLAMPING);
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return 0;
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}
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/* Must be called with clk disabled, and returns with clk enabled */
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int tegra_powergate_sequence_power_up(int id, struct clk *clk)
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{
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int ret;
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tegra_periph_reset_assert(clk);
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ret = tegra_powergate_power_on(id);
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if (ret)
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goto err_power;
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ret = clk_prepare_enable(clk);
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if (ret)
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goto err_clk;
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udelay(10);
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ret = tegra_powergate_remove_clamping(id);
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if (ret)
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goto err_clamp;
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udelay(10);
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tegra_periph_reset_deassert(clk);
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return 0;
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err_clamp:
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clk_disable_unprepare(clk);
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err_clk:
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tegra_powergate_power_off(id);
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err_power:
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return ret;
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}
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int tegra_cpu_powergate_id(int cpuid)
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{
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if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
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return tegra_cpu_domains[cpuid];
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return -EINVAL;
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}
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int __init tegra_powergate_init(void)
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{
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switch (tegra_chip_id) {
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case TEGRA20:
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tegra_num_powerdomains = 7;
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break;
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case TEGRA30:
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tegra_num_powerdomains = 14;
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tegra_num_cpu_domains = 4;
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tegra_cpu_domains = tegra30_cpu_domains;
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break;
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default:
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/* Unknown Tegra variant. Disable powergating */
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tegra_num_powerdomains = 0;
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break;
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}
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static const char * const *powergate_name;
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static const char * const powergate_name_t20[] = {
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[TEGRA_POWERGATE_CPU] = "cpu",
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[TEGRA_POWERGATE_3D] = "3d",
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[TEGRA_POWERGATE_VENC] = "venc",
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[TEGRA_POWERGATE_VDEC] = "vdec",
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[TEGRA_POWERGATE_PCIE] = "pcie",
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[TEGRA_POWERGATE_L2] = "l2",
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[TEGRA_POWERGATE_MPE] = "mpe",
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};
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static const char * const powergate_name_t30[] = {
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[TEGRA_POWERGATE_CPU] = "cpu0",
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[TEGRA_POWERGATE_3D] = "3d0",
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[TEGRA_POWERGATE_VENC] = "venc",
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[TEGRA_POWERGATE_VDEC] = "vdec",
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[TEGRA_POWERGATE_PCIE] = "pcie",
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[TEGRA_POWERGATE_L2] = "l2",
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[TEGRA_POWERGATE_MPE] = "mpe",
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[TEGRA_POWERGATE_HEG] = "heg",
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[TEGRA_POWERGATE_SATA] = "sata",
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[TEGRA_POWERGATE_CPU1] = "cpu1",
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[TEGRA_POWERGATE_CPU2] = "cpu2",
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[TEGRA_POWERGATE_CPU3] = "cpu3",
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[TEGRA_POWERGATE_CELP] = "celp",
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[TEGRA_POWERGATE_3D1] = "3d1",
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};
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static int powergate_show(struct seq_file *s, void *data)
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{
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int i;
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seq_printf(s, " powergate powered\n");
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seq_printf(s, "------------------\n");
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for (i = 0; i < tegra_num_powerdomains; i++)
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seq_printf(s, " %9s %7s\n", powergate_name[i],
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tegra_powergate_is_powered(i) ? "yes" : "no");
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return 0;
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}
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static int powergate_open(struct inode *inode, struct file *file)
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{
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return single_open(file, powergate_show, inode->i_private);
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}
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static const struct file_operations powergate_fops = {
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.open = powergate_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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int __init tegra_powergate_debugfs_init(void)
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{
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struct dentry *d;
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switch (tegra_chip_id) {
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case TEGRA20:
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powergate_name = powergate_name_t20;
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break;
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case TEGRA30:
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powergate_name = powergate_name_t30;
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break;
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}
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if (powergate_name) {
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d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
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&powergate_fops);
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if (!d)
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return -ENOMEM;
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}
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return 0;
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}
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#endif
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