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The tegra_cpu_car_ops provide the interface for CPU to control it's clock gating and reset status. The other drivers should use this for CPU control. And should not directly access CAR registers to control CPU. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
169 lines
3.7 KiB
C
169 lines
3.7 KiB
C
/*
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*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <mach/clk.h>
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#include "board.h"
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#include "clock.h"
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#include "tegra_cpu_car.h"
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/* Global data of Tegra CPU CAR ops */
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struct tegra_cpu_car_ops *tegra_cpu_car_ops;
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/*
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* Locking:
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*
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* An additional mutex, clock_list_lock, is used to protect the list of all
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* clocks.
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*
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*/
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static DEFINE_MUTEX(clock_list_lock);
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static LIST_HEAD(clocks);
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void tegra_clk_add(struct clk *clk)
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{
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struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
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mutex_lock(&clock_list_lock);
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list_add(&c->node, &clocks);
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mutex_unlock(&clock_list_lock);
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}
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struct clk *tegra_get_clock_by_name(const char *name)
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{
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struct clk_tegra *c;
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struct clk *ret = NULL;
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mutex_lock(&clock_list_lock);
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list_for_each_entry(c, &clocks, node) {
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if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
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ret = c->hw.clk;
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break;
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}
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}
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mutex_unlock(&clock_list_lock);
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return ret;
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}
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static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
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{
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struct clk *c;
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struct clk *p;
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struct clk *parent;
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int ret = 0;
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c = tegra_get_clock_by_name(table->name);
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if (!c) {
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pr_warn("Unable to initialize clock %s\n",
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table->name);
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return -ENODEV;
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}
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parent = clk_get_parent(c);
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if (table->parent) {
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p = tegra_get_clock_by_name(table->parent);
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if (!p) {
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pr_warn("Unable to find parent %s of clock %s\n",
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table->parent, table->name);
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return -ENODEV;
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}
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if (parent != p) {
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ret = clk_set_parent(c, p);
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if (ret) {
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pr_warn("Unable to set parent %s of clock %s: %d\n",
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table->parent, table->name, ret);
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return -EINVAL;
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}
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}
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}
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if (table->rate && table->rate != clk_get_rate(c)) {
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ret = clk_set_rate(c, table->rate);
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if (ret) {
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pr_warn("Unable to set clock %s to rate %lu: %d\n",
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table->name, table->rate, ret);
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return -EINVAL;
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}
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}
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if (table->enabled) {
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ret = clk_prepare_enable(c);
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if (ret) {
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pr_warn("Unable to enable clock %s: %d\n",
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table->name, ret);
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return -EINVAL;
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}
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}
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return 0;
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}
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void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
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{
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for (; table->name; table++)
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tegra_clk_init_one_from_table(table);
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}
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void tegra_periph_reset_deassert(struct clk *c)
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{
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struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
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BUG_ON(!clk->reset);
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clk->reset(__clk_get_hw(c), false);
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}
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EXPORT_SYMBOL(tegra_periph_reset_deassert);
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void tegra_periph_reset_assert(struct clk *c)
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{
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struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
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BUG_ON(!clk->reset);
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clk->reset(__clk_get_hw(c), true);
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}
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EXPORT_SYMBOL(tegra_periph_reset_assert);
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/* Several extended clock configuration bits (e.g., clock routing, clock
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* phase control) are included in PLL and peripheral clock source
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* registers. */
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int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
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{
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int ret = 0;
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struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
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if (!clk->clk_cfg_ex) {
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ret = -ENOSYS;
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goto out;
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}
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ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
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out:
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return ret;
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}
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