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Platform data is used to specify controller hardware specific information such as the tx/rx fifo level mask and bit offset of rx fifo level. Such information is not suitable to be supplied from device tree. Instead, it can be moved into the driver data and removed from platform data. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
175 lines
4.1 KiB
C
175 lines
4.1 KiB
C
/* linux/arch/arm/mach-s3c2416/clock.c
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*
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* Copyright (c) 2010 Simtec Electronics
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* Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
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*
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* S3C2416 Clock control support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <plat/s3c2416.h>
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq.h>
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#include <plat/pll.h>
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#include <asm/mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-s3c2443-clock.h>
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/* armdiv
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*
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* this clock is sourced from msysclk and can have a number of
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* divider values applied to it to then be fed into armclk.
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* The real clock definition is done in s3c2443-clock.c,
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* only the armdiv divisor table must be defined here.
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*/
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static unsigned int armdiv[8] = {
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[0] = 1,
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[1] = 2,
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[2] = 3,
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[3] = 4,
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[5] = 6,
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[7] = 8,
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};
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static struct clksrc_clk hsspi_eplldiv = {
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.clk = {
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.name = "hsspi-eplldiv",
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.parent = &clk_esysclk.clk,
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.ctrlbit = (1 << 14),
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.enable = s3c2443_clkcon_enable_s,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
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};
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static struct clk *hsspi_sources[] = {
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[0] = &hsspi_eplldiv.clk,
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[1] = NULL, /* to fix */
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};
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static struct clksrc_clk hsspi_mux = {
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.clk = {
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.name = "hsspi-if",
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},
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.sources = &(struct clksrc_sources) {
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.sources = hsspi_sources,
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.nr_sources = ARRAY_SIZE(hsspi_sources),
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
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};
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static struct clksrc_clk hsmmc_div[] = {
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[0] = {
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.clk = {
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.name = "hsmmc-div",
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.devname = "s3c-sdhci.0",
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
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},
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[1] = {
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.clk = {
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.name = "hsmmc-div",
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.devname = "s3c-sdhci.1",
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.parent = &clk_esysclk.clk,
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},
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.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
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},
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};
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static struct clksrc_clk hsmmc_mux0 = {
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.clk = {
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.name = "hsmmc-if",
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.devname = "s3c-sdhci.0",
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.ctrlbit = (1 << 6),
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.enable = s3c2443_clkcon_enable_s,
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},
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.sources = &(struct clksrc_sources) {
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.nr_sources = 2,
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.sources = (struct clk * []) {
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[0] = &hsmmc_div[0].clk,
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[1] = NULL, /* to fix */
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},
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
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};
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static struct clksrc_clk hsmmc_mux1 = {
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.clk = {
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.name = "hsmmc-if",
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.devname = "s3c-sdhci.1",
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.ctrlbit = (1 << 12),
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.enable = s3c2443_clkcon_enable_s,
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},
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.sources = &(struct clksrc_sources) {
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.nr_sources = 2,
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.sources = (struct clk * []) {
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[0] = &hsmmc_div[1].clk,
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[1] = NULL, /* to fix */
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},
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},
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.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
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};
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static struct clk hsmmc0_clk = {
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.name = "hsmmc",
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.devname = "s3c-sdhci.0",
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.parent = &clk_h,
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.enable = s3c2443_clkcon_enable_h,
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.ctrlbit = S3C2416_HCLKCON_HSMMC0,
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};
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static struct clksrc_clk *clksrcs[] __initdata = {
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&hsspi_eplldiv,
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&hsspi_mux,
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&hsmmc_div[0],
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&hsmmc_div[1],
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&hsmmc_mux0,
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&hsmmc_mux1,
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};
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static struct clk_lookup s3c2416_clk_lookup[] = {
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
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CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
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CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
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/* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
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CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
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};
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void __init s3c2416_init_clocks(int xtal)
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{
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u32 epllcon = __raw_readl(S3C2443_EPLLCON);
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u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
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int ptr;
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/* s3c2416 EPLL compatible with s3c64xx */
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clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
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clk_epll.parent = &clk_epllref.clk;
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s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
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armdiv, ARRAY_SIZE(armdiv),
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S3C2416_CLKDIV0_ARMDIV_MASK);
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for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
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s3c_register_clksrc(clksrcs[ptr], 1);
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s3c24xx_register_clock(&hsmmc0_clk);
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clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
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s3c_pwmclk_init();
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}
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