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4b25408f1f
This way we can remove includes of plat/gpio.h which won't work with the single zImage support. Note that we also remove the cpu_class_is_omap2() check in gpio-omap.c as the drivers should not call it as we need to make it local to arch/arm/mach-omap2 for single zImage support. While at it, arrange the related includes in the standard way. Cc: Grant Likely <grant.likely@secretlab.ca> Cc: linux-mtd@lists.infradead.org Cc: alsa-devel@alsa-project.org Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
163 lines
4.7 KiB
C
163 lines
4.7 KiB
C
/*
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* MSDI IP block reset
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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* XXX What about pad muxing?
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/platform_data/gpio-omap.h>
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#include <plat/omap_hwmod.h>
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#include <plat/omap_device.h>
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#include <plat/mmc.h>
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#include "common.h"
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#include "control.h"
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#include "mux.h"
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/*
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* MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
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* from the IP block's base address
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*/
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#define MSDI_CON_OFFSET 0x0c
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/* Register bitfields in the CON register */
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#define MSDI_CON_POW_MASK BIT(11)
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#define MSDI_CON_CLKD_MASK (0x3f << 0)
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#define MSDI_CON_CLKD_SHIFT 0
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/* Maximum microseconds to wait for OMAP module to softreset */
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#define MAX_MODULE_SOFTRESET_WAIT 10000
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/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
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#define MSDI_TARGET_RESET_CLKD 0x3ff
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/**
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* omap_msdi_reset - reset the MSDI IP block
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* @oh: struct omap_hwmod *
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*
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* The MSDI IP block on OMAP2420 has to have both the POW and CLKD
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* fields set inside its CON register for a reset to complete
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* successfully. This is not documented in the TRM. For CLKD, we use
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* the value that results in the lowest possible clock rate, to attempt
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* to avoid disturbing any cards.
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*/
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int omap_msdi_reset(struct omap_hwmod *oh)
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{
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u16 v = 0;
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int c = 0;
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/* Write to the SOFTRESET bit */
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omap_hwmod_softreset(oh);
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/* Enable the MSDI core and internal clock */
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v |= MSDI_CON_POW_MASK;
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v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
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omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
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/* Poll on RESETDONE bit */
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omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
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& SYSS_RESETDONE_MASK),
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MAX_MODULE_SOFTRESET_WAIT, c);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warning("%s: %s: softreset failed (waited %d usec)\n",
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__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
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else
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pr_debug("%s: %s: softreset in %d usec\n", __func__,
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oh->name, c);
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/* Disable the MSDI internal clock */
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v &= ~MSDI_CON_CLKD_MASK;
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omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
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return 0;
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}
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#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
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static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
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*mmc_controller)
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{
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if ((mmc_controller->slots[0].switch_pin > 0) && \
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(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
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omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
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OMAP_PIN_INPUT_PULLUP);
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if ((mmc_controller->slots[0].gpio_wp > 0) && \
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(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
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omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc_cmd", 0);
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omap_mux_init_signal("sdmmc_clki", 0);
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omap_mux_init_signal("sdmmc_clko", 0);
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omap_mux_init_signal("sdmmc_dat0", 0);
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omap_mux_init_signal("sdmmc_dat_dir0", 0);
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omap_mux_init_signal("sdmmc_cmd_dir", 0);
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if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
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omap_mux_init_signal("sdmmc_dat1", 0);
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omap_mux_init_signal("sdmmc_dat2", 0);
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omap_mux_init_signal("sdmmc_dat3", 0);
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omap_mux_init_signal("sdmmc_dat_dir1", 0);
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omap_mux_init_signal("sdmmc_dat_dir2", 0);
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omap_mux_init_signal("sdmmc_dat_dir3", 0);
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}
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/*
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* Use internal loop-back in MMC/SDIO Module Input Clock
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* selection
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*/
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if (mmc_controller->slots[0].internal_clock) {
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u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
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v |= (1 << 24);
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omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
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}
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}
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void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
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{
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struct platform_device *pdev;
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struct omap_hwmod *oh;
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int id = 0;
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char *oh_name = "msdi1";
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char *dev_name = "mmci-omap";
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if (!mmc_data[0]) {
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pr_err("%s fails: Incomplete platform data\n", __func__);
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return;
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}
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omap242x_mmc_mux(mmc_data[0]);
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oh = omap_hwmod_lookup(oh_name);
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if (!oh) {
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pr_err("Could not look up %s\n", oh_name);
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return;
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}
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pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
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sizeof(struct omap_mmc_platform_data), NULL, 0, 0);
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if (IS_ERR(pdev))
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WARN(1, "Can'd build omap_device for %s:%s.\n",
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dev_name, oh->name);
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}
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#endif
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