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c09fcc438c
Found by http://coccinelle.lip6.fr/ Signed-off-by: Peter Senna Tschudin <peter.senna@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
533 lines
15 KiB
C
533 lines
15 KiB
C
/*
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* clkt_clksel.c - OMAP2/3/4 clksel clock functions
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*
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* clksel clocks are clocks that do not have a fixed parent, or that
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* can divide their parent's rate, or possibly both at the same time, based
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* on the contents of a hardware register bitfield.
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*
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* All of the various mux and divider settings can be encoded into
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* struct clksel* data structures, and then these can be autogenerated
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* from some hardware database for each new chip generation. This
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* should avoid the need to write, review, and validate a lot of new
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* clock code for each new chip, since it can be exported from the SoC
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* design flow. This is now done on OMAP4.
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*
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* The fusion of mux and divider clocks is a software creation. In
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* hardware reality, the multiplexer (parent selection) and the
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* divider exist separately. XXX At some point these clksel clocks
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* should be split into "divider" clocks and "mux" clocks to better
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* match the hardware.
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*
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* (The name "clksel" comes from the name of the corresponding
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* register field in the OMAP2/3 family of SoCs.)
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*
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* XXX Currently these clocks are only used in the OMAP2/3/4 code, but
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* many of the OMAP1 clocks should be convertible to use this
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* mechanism.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/bug.h>
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#include <plat/clock.h>
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#include "clock.h"
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/* Private functions */
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/**
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* _get_clksel_by_parent() - return clksel struct for a given clk & parent
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* @clk: OMAP struct clk ptr to inspect
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* @src_clk: OMAP struct clk ptr of the parent clk to search for
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*
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* Scan the struct clksel array associated with the clock to find
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* the element associated with the supplied parent clock address.
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* Returns a pointer to the struct clksel on success or NULL on error.
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*/
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static const struct clksel *_get_clksel_by_parent(struct clk *clk,
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struct clk *src_clk)
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{
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const struct clksel *clks;
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for (clks = clk->clksel; clks->parent; clks++)
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if (clks->parent == src_clk)
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break; /* Found the requested parent */
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if (!clks->parent) {
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/* This indicates a data problem */
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WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
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__clk_get_name(clk), __clk_get_name(src_clk));
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return NULL;
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}
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return clks;
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}
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/**
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* _get_div_and_fieldval() - find the new clksel divisor and field value to use
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* @src_clk: planned new parent struct clk *
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* @clk: struct clk * that is being reparented
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* @field_val: pointer to a u32 to contain the register data for the divisor
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*
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* Given an intended new parent struct clk * @src_clk, and the struct
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* clk * @clk to the clock that is being reparented, find the
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* appropriate rate divisor for the new clock (returned as the return
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* value), and the corresponding register bitfield data to program to
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* reach that divisor (returned in the u32 pointed to by @field_val).
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* Returns 0 on error, or returns the newly-selected divisor upon
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* success (in this latter case, the corresponding register bitfield
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* value is passed back in the variable pointed to by @field_val)
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*/
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static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
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u32 *field_val)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr, *max_clkr = NULL;
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u8 max_div = 0;
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clks = _get_clksel_by_parent(clk, src_clk);
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if (!clks)
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return 0;
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/*
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* Find the highest divisor (e.g., the one resulting in the
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* lowest rate) to use as the default. This should avoid
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* clock rates that are too high for the device. XXX A better
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* solution here would be to try to determine if there is a
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* divisor matching the original clock rate before the parent
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* switch, and if it cannot be found, to fall back to the
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* highest divisor.
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*/
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for (clkr = clks->rates; clkr->div; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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if (clkr->div > max_div) {
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max_div = clkr->div;
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max_clkr = clkr;
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}
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}
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if (max_div == 0) {
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/* This indicates an error in the clksel data */
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WARN(1, "clock: %s: could not find divisor for parent %s\n",
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__clk_get_name(clk),
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__clk_get_name(__clk_get_parent(src_clk)));
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return 0;
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}
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*field_val = max_clkr->val;
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return max_div;
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}
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/**
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* _write_clksel_reg() - program a clock's clksel register in hardware
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* @clk: struct clk * to program
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* @v: clksel bitfield value to program (with LSB at bit 0)
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*
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* Shift the clksel register bitfield value @v to its appropriate
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* location in the clksel register and write it in. This function
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* will ensure that the write to the clksel_reg reaches its
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* destination before returning -- important since PRM and CM register
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* accesses can be quite slow compared to ARM cycles -- but does not
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* take into account any time the hardware might take to switch the
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* clock source.
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*/
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static void _write_clksel_reg(struct clk *clk, u32 field_val)
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{
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u32 v;
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v = __raw_readl(clk->clksel_reg);
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v &= ~clk->clksel_mask;
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v |= field_val << __ffs(clk->clksel_mask);
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__raw_writel(v, clk->clksel_reg);
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v = __raw_readl(clk->clksel_reg); /* OCP barrier */
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}
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/**
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* _clksel_to_divisor() - turn clksel field value into integer divider
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* @clk: OMAP struct clk to use
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* @field_val: register field value to find
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*
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* Given a struct clk of a rate-selectable clksel clock, and a register field
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* value to search for, find the corresponding clock divisor. The register
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* field value should be pre-masked and shifted down so the LSB is at bit 0
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* before calling. Returns 0 on error or returns the actual integer divisor
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* upon success.
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*/
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static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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struct clk *parent;
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parent = __clk_get_parent(clk);
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clks = _get_clksel_by_parent(clk, parent);
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if (!clks)
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return 0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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if (clkr->val == field_val)
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break;
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}
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if (!clkr->div) {
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/* This indicates a data error */
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WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
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__clk_get_name(clk), field_val, __clk_get_name(parent));
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return 0;
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}
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return clkr->div;
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}
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/**
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* _divisor_to_clksel() - turn clksel integer divisor into a field value
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* @clk: OMAP struct clk to use
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* @div: integer divisor to search for
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*
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* Given a struct clk of a rate-selectable clksel clock, and a clock
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* divisor, find the corresponding register field value. Returns the
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* register field value _before_ left-shifting (i.e., LSB is at bit
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* 0); or returns 0xFFFFFFFF (~0) upon error.
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*/
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static u32 _divisor_to_clksel(struct clk *clk, u32 div)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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struct clk *parent;
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/* should never happen */
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WARN_ON(div == 0);
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parent = __clk_get_parent(clk);
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clks = _get_clksel_by_parent(clk, parent);
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if (!clks)
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return ~0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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if (clkr->div == div)
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break;
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}
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if (!clkr->div) {
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pr_err("clock: %s: could not find divisor %d for parent %s\n",
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__clk_get_name(clk), div, __clk_get_name(parent));
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return ~0;
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}
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return clkr->val;
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}
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/**
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* _read_divisor() - get current divisor applied to parent clock (from hdwr)
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* @clk: OMAP struct clk to use.
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*
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* Read the current divisor register value for @clk that is programmed
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* into the hardware, convert it into the actual divisor value, and
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* return it; or return 0 on error.
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*/
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static u32 _read_divisor(struct clk *clk)
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{
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u32 v;
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if (!clk->clksel || !clk->clksel_mask)
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return 0;
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v = __raw_readl(clk->clksel_reg);
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v &= clk->clksel_mask;
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v >>= __ffs(clk->clksel_mask);
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return _clksel_to_divisor(clk, v);
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}
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/* Public functions */
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/**
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* omap2_clksel_round_rate_div() - find divisor for the given clock and rate
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* @clk: OMAP struct clk to use
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* @target_rate: desired clock rate
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* @new_div: ptr to where we should store the divisor
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*
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* Finds 'best' divider value in an array based on the source and target
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* rates. The divider array must be sorted with smallest divider first.
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* This function is also used by the DPLL3 M2 divider code.
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*
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* Returns the rounded clock rate or returns 0xffffffff on error.
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*/
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u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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u32 *new_div)
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{
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unsigned long test_rate;
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 last_div = 0;
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struct clk *parent;
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unsigned long parent_rate;
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const char *clk_name;
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parent = __clk_get_parent(clk);
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parent_rate = __clk_get_rate(parent);
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clk_name = __clk_get_name(clk);
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if (!clk->clksel || !clk->clksel_mask)
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return ~0;
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pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
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clk_name, target_rate);
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*new_div = 1;
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clks = _get_clksel_by_parent(clk, parent);
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if (!clks)
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return ~0;
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for (clkr = clks->rates; clkr->div; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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/* Sanity check */
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if (clkr->div <= last_div)
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pr_err("clock: %s: clksel_rate table not sorted\n",
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clk_name);
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last_div = clkr->div;
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test_rate = parent_rate / clkr->div;
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if (test_rate <= target_rate)
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break; /* found it */
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}
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if (!clkr->div) {
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pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
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clk_name, target_rate, __clk_get_name(parent));
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return ~0;
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}
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*new_div = clkr->div;
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pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
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(parent_rate / clkr->div));
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return parent_rate / clkr->div;
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}
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/*
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* Clocktype interface functions to the OMAP clock code
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* (i.e., those used in struct clk field function pointers, etc.)
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*/
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/**
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* omap2_init_clksel_parent() - set a clksel clk's parent field from the hdwr
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* @clk: OMAP clock struct ptr to use
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*
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* Given a pointer @clk to a source-selectable struct clk, read the
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* hardware register and determine what its parent is currently set
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* to. Update @clk's .parent field with the appropriate clk ptr. No
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* return value.
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*/
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void omap2_init_clksel_parent(struct clk *clk)
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{
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const struct clksel *clks;
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const struct clksel_rate *clkr;
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u32 r, found = 0;
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struct clk *parent;
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const char *clk_name;
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if (!clk->clksel || !clk->clksel_mask)
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return;
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parent = __clk_get_parent(clk);
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clk_name = __clk_get_name(clk);
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r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
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r >>= __ffs(clk->clksel_mask);
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for (clks = clk->clksel; clks->parent && !found; clks++) {
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for (clkr = clks->rates; clkr->div && !found; clkr++) {
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if (!(clkr->flags & cpu_mask))
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continue;
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if (clkr->val == r) {
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if (parent != clks->parent) {
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pr_debug("clock: %s: inited parent to %s (was %s)\n",
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clk_name,
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__clk_get_name(clks->parent),
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((parent) ?
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__clk_get_name(parent) :
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"NULL"));
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clk_reparent(clk, clks->parent);
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}
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found = 1;
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}
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}
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}
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/* This indicates a data error */
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WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
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clk_name, r);
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return;
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}
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/**
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* omap2_clksel_recalc() - function ptr to pass via struct clk .recalc field
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* @clk: struct clk *
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*
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* This function is intended to be called only by the clock framework.
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* Each clksel clock should have its struct clk .recalc field set to this
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* function. Returns the clock's current rate, based on its parent's rate
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* and its current divisor setting in the hardware.
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*/
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unsigned long omap2_clksel_recalc(struct clk *clk)
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{
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unsigned long rate;
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u32 div = 0;
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struct clk *parent;
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div = _read_divisor(clk);
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if (div == 0)
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return __clk_get_rate(clk);
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parent = __clk_get_parent(clk);
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rate = __clk_get_rate(parent) / div;
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pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
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__clk_get_name(clk), rate, div);
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return rate;
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}
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/**
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* omap2_clksel_round_rate() - find rounded rate for the given clock and rate
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* @clk: OMAP struct clk to use
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* @target_rate: desired clock rate
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*
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* This function is intended to be called only by the clock framework.
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* Finds best target rate based on the source clock and possible dividers.
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* rates. The divider array must be sorted with smallest divider first.
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*
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* Returns the rounded clock rate or returns 0xffffffff on error.
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*/
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long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
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{
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u32 new_div;
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return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
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}
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/**
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* omap2_clksel_set_rate() - program clock rate in hardware
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* @clk: struct clk * to program rate
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* @rate: target rate to program
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*
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* This function is intended to be called only by the clock framework.
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* Program @clk's rate to @rate in the hardware. The clock can be
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* either enabled or disabled when this happens, although if the clock
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* is enabled, some downstream devices may glitch or behave
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* unpredictably when the clock rate is changed - this depends on the
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* hardware. This function does not currently check the usecount of
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* the clock, so if multiple drivers are using the clock, and the rate
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* is changed, they will all be affected without any notification.
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* Returns -EINVAL upon error, or 0 upon success.
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*/
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int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 field_val, validrate, new_div = 0;
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if (!clk->clksel || !clk->clksel_mask)
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return -EINVAL;
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validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
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if (validrate != rate)
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return -EINVAL;
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field_val = _divisor_to_clksel(clk, new_div);
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if (field_val == ~0)
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return -EINVAL;
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_write_clksel_reg(clk, field_val);
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clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
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pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
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__clk_get_rate(clk));
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return 0;
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}
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/*
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* Clksel parent setting function - not passed in struct clk function
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* pointer - instead, the OMAP clock code currently assumes that any
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* parent-setting clock is a clksel clock, and calls
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* omap2_clksel_set_parent() by default
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*/
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/**
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* omap2_clksel_set_parent() - change a clock's parent clock
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* @clk: struct clk * of the child clock
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* @new_parent: struct clk * of the new parent clock
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*
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* This function is intended to be called only by the clock framework.
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* Change the parent clock of clock @clk to @new_parent. This is
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* intended to be used while @clk is disabled. This function does not
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* currently check the usecount of the clock, so if multiple drivers
|
|
* are using the clock, and the parent is changed, they will all be
|
|
* affected without any notification. Returns -EINVAL upon error, or
|
|
* 0 upon success.
|
|
*/
|
|
int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
|
|
{
|
|
u32 field_val = 0;
|
|
u32 parent_div;
|
|
|
|
if (!clk->clksel || !clk->clksel_mask)
|
|
return -EINVAL;
|
|
|
|
parent_div = _get_div_and_fieldval(new_parent, clk, &field_val);
|
|
if (!parent_div)
|
|
return -EINVAL;
|
|
|
|
_write_clksel_reg(clk, field_val);
|
|
|
|
clk_reparent(clk, new_parent);
|
|
|
|
/* CLKSEL clocks follow their parents' rates, divided by a divisor */
|
|
clk->rate = __clk_get_rate(new_parent);
|
|
|
|
if (parent_div > 0)
|
|
__clk_get_rate(clk) /= parent_div;
|
|
|
|
pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
|
|
__clk_get_name(clk),
|
|
__clk_get_name(__clk_get_parent(clk)),
|
|
__clk_get_rate(clk));
|
|
|
|
return 0;
|
|
}
|