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5dcc3b975e
While we move to Common Clk Framework (CCF), direct deferencing of struct clk wouldn't be possible anymore. Hence get rid of all such instances in the current clock code and use macros/helpers similar to the ones that are provided by CCF. While here also concatenate some strings split across multiple lines which seem to be needed anyway. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: simplified some compound expressions; reformatted some messages] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Mike Turquette <mturquette@linaro.org>
172 lines
4.6 KiB
C
172 lines
4.6 KiB
C
/*
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* OMAP2xxx DVFS virtual clock functions
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*
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* Copyright (C) 2005-2008 Texas Instruments, Inc.
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* Copyright (C) 2004-2010 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
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* Gordon McNutt and RidgeRun, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* XXX Some of this code should be replaceable by the upcoming OPP layer
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* code. However, some notion of "rate set" is probably still necessary
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* for OMAP2xxx at least. Rate sets should be generalized so they can be
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* used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff
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* has in the past expressed a preference to use rate sets for OPP changes,
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* rather than dynamically recalculating the clock tree, so if someone wants
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* this badly enough to write the code to handle it, we should support it
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* as an option.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/cpufreq.h>
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#include <linux/slab.h>
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#include <plat/clock.h>
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#include <plat/sram.h>
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#include <plat/sdrc.h>
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#include "soc.h"
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#include "clock.h"
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#include "clock2xxx.h"
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#include "opp2xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
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const struct prcm_config *curr_prcm_set;
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const struct prcm_config *rate_table;
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/**
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* omap2_table_mpu_recalc - just return the MPU speed
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* @clk: virt_prcm_set struct clk
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*
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* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
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*/
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unsigned long omap2_table_mpu_recalc(struct clk *clk)
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{
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return curr_prcm_set->mpu_speed;
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}
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/*
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* Look for a rate equal or less than the target rate given a configuration set.
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*
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* What's not entirely clear is "which" field represents the key field.
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* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
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* just uses the ARM rates.
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*/
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long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
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{
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const struct prcm_config *ptr;
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long highest_rate, sys_clk_rate;
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highest_rate = -EINVAL;
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sys_clk_rate = __clk_get_rate(sclk);
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for (ptr = rate_table; ptr->mpu_speed; ptr++) {
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if (!(ptr->flags & cpu_mask))
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continue;
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if (ptr->xtal_speed != sys_clk_rate)
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continue;
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highest_rate = ptr->mpu_speed;
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/* Can check only after xtal frequency check */
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if (ptr->mpu_speed <= rate)
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break;
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}
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return highest_rate;
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}
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/* Sets basic clocks based on the specified rate */
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int omap2_select_table_rate(struct clk *clk, unsigned long rate)
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{
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u32 cur_rate, done_rate, bypass = 0, tmp;
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const struct prcm_config *prcm;
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unsigned long found_speed = 0;
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unsigned long flags;
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long sys_clk_rate;
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sys_clk_rate = __clk_get_rate(sclk);
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for (prcm = rate_table; prcm->mpu_speed; prcm++) {
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if (!(prcm->flags & cpu_mask))
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continue;
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if (prcm->xtal_speed != sys_clk_rate)
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continue;
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if (prcm->mpu_speed <= rate) {
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found_speed = prcm->mpu_speed;
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break;
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}
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}
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if (!found_speed) {
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printk(KERN_INFO "Could not set MPU rate to %luMHz\n",
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rate / 1000000);
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return -EINVAL;
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}
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curr_prcm_set = prcm;
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cur_rate = omap2xxx_clk_get_core_rate(dclk);
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if (prcm->dpll_speed == cur_rate / 2) {
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omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
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} else if (prcm->dpll_speed == cur_rate * 2) {
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omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
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} else if (prcm->dpll_speed != cur_rate) {
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local_irq_save(flags);
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if (prcm->dpll_speed == prcm->xtal_speed)
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bypass = 1;
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if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) ==
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CORE_CLK_SRC_DPLL_X2)
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done_rate = CORE_CLK_SRC_DPLL_X2;
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else
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done_rate = CORE_CLK_SRC_DPLL;
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/* MPU divider */
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omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
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/* dsp + iva1 div(2420), iva2.1(2430) */
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omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
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OMAP24XX_DSP_MOD, CM_CLKSEL);
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omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
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/* Major subsystem dividers */
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tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
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omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
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CM_CLKSEL1);
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if (cpu_is_omap2430())
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omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
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OMAP2430_MDM_MOD, CM_CLKSEL);
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/* x2 to enter omap2xxx_sdrc_init_params() */
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omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
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omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
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bypass);
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omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
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omap2xxx_sdrc_reprogram(done_rate, 0);
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local_irq_restore(flags);
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}
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return 0;
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}
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