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b8182832c5
DECON-TV IP is responsible for generating video stream which is transferred to HDMI IP. It is almost fully compatible with DECON IP. The patch is based on initial work of Hyungwon Hwang. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
195 lines
6.2 KiB
C
195 lines
6.2 KiB
C
/*
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* Copyright (C) 2014 Samsung Electronics Co.Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundationr
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*/
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#ifndef EXYNOS_REGS_DECON_H
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#define EXYNOS_REGS_DECON_H
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/* Exynos543X DECON */
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#define DECON_VIDCON0 0x0000
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#define DECON_VIDOUTCON0 0x0010
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#define DECON_WINCONx(n) (0x0020 + ((n) * 4))
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#define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4))
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#define DECON_SHADOWCON 0x00A0
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#define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20))
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#define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20))
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#define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20))
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#define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20))
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#define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20))
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#define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10))
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#define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10))
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#define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10))
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#define DECON_VIDW0xADD1B0(n) (0x01A0 + ((n) * 0x10))
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#define DECON_VIDW0xADD1B1(n) (0x01A4 + ((n) * 0x10))
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#define DECON_VIDW0xADD1B2(n) (0x01A8 + ((n) * 0x10))
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#define DECON_VIDW0xADD2(n) (0x0200 + ((n) * 4))
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#define DECON_LOCALxSIZE(n) (0x0214 + ((n) * 4))
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#define DECON_VIDINTCON0 0x0220
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#define DECON_VIDINTCON1 0x0224
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#define DECON_WxKEYCON0(n) (0x0230 + ((n - 1) * 8))
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#define DECON_WxKEYCON1(n) (0x0234 + ((n - 1) * 8))
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#define DECON_WxKEYALPHA(n) (0x0250 + ((n - 1) * 4))
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#define DECON_WINxMAP(n) (0x0270 + ((n) * 4))
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#define DECON_QOSLUT07_00 0x02C0
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#define DECON_QOSLUT15_08 0x02C4
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#define DECON_QOSCTRL 0x02C8
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#define DECON_BLENDERQx(n) (0x0300 + ((n - 1) * 4))
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#define DECON_BLENDCON 0x0310
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#define DECON_OPE_VIDW0xADD0(n) (0x0400 + ((n) * 4))
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#define DECON_OPE_VIDW0xADD1(n) (0x0414 + ((n) * 4))
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#define DECON_FRAMEFIFO_REG7 0x051C
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#define DECON_FRAMEFIFO_REG8 0x0520
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#define DECON_FRAMEFIFO_STATUS 0x0524
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#define DECON_CMU 0x1404
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#define DECON_UPDATE 0x1410
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#define DECON_UPDATE_SCHEME 0x1438
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#define DECON_VIDCON1 0x2000
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#define DECON_VIDCON2 0x2004
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#define DECON_VIDCON3 0x2008
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#define DECON_VIDCON4 0x200C
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#define DECON_VIDTCON2 0x2028
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#define DECON_FRAME_SIZE 0x2038
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#define DECON_LINECNT_OP_THRESHOLD 0x203C
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#define DECON_TRIGCON 0x2040
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#define DECON_TRIGSKIP 0x2050
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#define DECON_CRCRDATA 0x20B0
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#define DECON_CRCCTRL 0x20B4
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/* Exynos5430 DECON */
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#define DECON_VIDTCON0 0x2020
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#define DECON_VIDTCON1 0x2024
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/* Exynos5433 DECON */
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#define DECON_VIDTCON00 0x2010
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#define DECON_VIDTCON01 0x2014
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#define DECON_VIDTCON10 0x2018
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#define DECON_VIDTCON11 0x201C
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/* Exynos543X DECON Internal */
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#define DECON_W013DSTREOCON 0x0320
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#define DECON_W233DSTREOCON 0x0324
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#define DECON_FRAMEFIFO_REG0 0x0500
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#define DECON_ENHANCER_CTRL 0x2100
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/* Exynos543X DECON TV */
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#define DECON_VCLKCON0 0x0014
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#define DECON_VIDINTCON2 0x0228
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#define DECON_VIDINTCON3 0x022C
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/* VIDCON0 */
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#define VIDCON0_SWRESET (1 << 28)
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#define VIDCON0_CLKVALUP (1 << 14)
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#define VIDCON0_VLCKFREE (1 << 5)
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#define VIDCON0_STOP_STATUS (1 << 2)
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#define VIDCON0_ENVID (1 << 1)
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#define VIDCON0_ENVID_F (1 << 0)
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/* VIDOUTCON0 */
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#define VIDOUT_LCD_ON (1 << 24)
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#define VIDOUT_IF_F_MASK (0x3 << 20)
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#define VIDOUT_RGB_IF (0x0 << 20)
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#define VIDOUT_COMMAND_IF (0x2 << 20)
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/* WINCONx */
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#define WINCONx_HAWSWP_F (1 << 16)
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#define WINCONx_WSWP_F (1 << 15)
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#define WINCONx_BURSTLEN_MASK (0x3 << 10)
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#define WINCONx_BURSTLEN_16WORD (0x0 << 10)
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#define WINCONx_BURSTLEN_8WORD (0x1 << 10)
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#define WINCONx_BURSTLEN_4WORD (0x2 << 10)
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#define WINCONx_BLD_PIX_F (1 << 6)
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#define WINCONx_BPPMODE_MASK (0xf << 2)
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#define WINCONx_BPPMODE_16BPP_565 (0x5 << 2)
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#define WINCONx_BPPMODE_16BPP_A1555 (0x6 << 2)
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#define WINCONx_BPPMODE_16BPP_I1555 (0x7 << 2)
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#define WINCONx_BPPMODE_24BPP_888 (0xb << 2)
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#define WINCONx_BPPMODE_24BPP_A1887 (0xc << 2)
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#define WINCONx_BPPMODE_25BPP_A1888 (0xd << 2)
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#define WINCONx_BPPMODE_32BPP_A8888 (0xd << 2)
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#define WINCONx_BPPMODE_16BPP_A4444 (0xe << 2)
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#define WINCONx_ALPHA_SEL_F (1 << 1)
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#define WINCONx_ENWIN_F (1 << 0)
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/* SHADOWCON */
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#define SHADOWCON_Wx_PROTECT(n) (1 << (10 + (n)))
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/* VIDOSDxD */
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#define VIDOSD_Wx_ALPHA_R_F(n) (((n) & 0xff) << 16)
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#define VIDOSD_Wx_ALPHA_G_F(n) (((n) & 0xff) << 8)
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#define VIDOSD_Wx_ALPHA_B_F(n) (((n) & 0xff) << 0)
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/* VIDINTCON0 */
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#define VIDINTCON0_FRAMEDONE (1 << 17)
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#define VIDINTCON0_INTFRMEN (1 << 12)
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#define VIDINTCON0_INTEN (1 << 0)
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/* VIDINTCON1 */
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#define VIDINTCON1_INTFRMDONEPEND (1 << 2)
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#define VIDINTCON1_INTFRMPEND (1 << 1)
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#define VIDINTCON1_INTFIFOPEND (1 << 0)
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/* DECON_CMU */
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#define CMU_CLKGAGE_MODE_SFR_F (1 << 1)
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#define CMU_CLKGAGE_MODE_MEM_F (1 << 0)
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/* DECON_UPDATE */
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#define STANDALONE_UPDATE_F (1 << 0)
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/* DECON_VIDCON1 */
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#define VIDCON1_VCLK_MASK (0x3 << 9)
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#define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9)
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#define VIDCON1_VCLK_HOLD (0x0 << 9)
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#define VIDCON1_VCLK_RUN (0x1 << 9)
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/* DECON_VIDTCON00 */
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#define VIDTCON00_VBPD_F(x) (((x) & 0xfff) << 16)
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#define VIDTCON00_VFPD_F(x) ((x) & 0xfff)
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/* DECON_VIDTCON01 */
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#define VIDTCON01_VSPW_F(x) (((x) & 0xfff) << 16)
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/* DECON_VIDTCON10 */
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#define VIDTCON10_HBPD_F(x) (((x) & 0xfff) << 16)
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#define VIDTCON10_HFPD_F(x) ((x) & 0xfff)
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/* DECON_VIDTCON11 */
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#define VIDTCON11_HSPW_F(x) (((x) & 0xfff) << 16)
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/* DECON_VIDTCON2 */
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#define VIDTCON2_LINEVAL(x) (((x) & 0xfff) << 16)
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#define VIDTCON2_HOZVAL(x) ((x) & 0xfff)
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/* TRIGCON */
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#define TRIGCON_TRIGEN_PER_F (1 << 31)
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#define TRIGCON_TRIGEN_F (1 << 30)
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#define TRIGCON_TE_AUTO_MASK (1 << 29)
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#define TRIGCON_WB_SWTRIGCMD (1 << 28)
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#define TRIGCON_SWTRIGCMD_W4BUF (1 << 26)
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#define TRIGCON_TRIGMODE_W4BUF (1 << 25)
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#define TRIGCON_SWTRIGCMD_W3BUF (1 << 21)
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#define TRIGCON_TRIGMODE_W3BUF (1 << 20)
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#define TRIGCON_SWTRIGCMD_W2BUF (1 << 16)
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#define TRIGCON_TRIGMODE_W2BUF (1 << 15)
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#define TRIGCON_SWTRIGCMD_W1BUF (1 << 11)
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#define TRIGCON_TRIGMODE_W1BUF (1 << 10)
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#define TRIGCON_SWTRIGCMD_W0BUF (1 << 6)
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#define TRIGCON_TRIGMODE_W0BUF (1 << 5)
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#define TRIGCON_HWTRIGMASK_I80_RGB (1 << 4)
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#define TRIGCON_HWTRIGEN_I80_RGB (1 << 3)
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#define TRIGCON_HWTRIG_INV_I80_RGB (1 << 2)
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#define TRIGCON_SWTRIGCMD (1 << 1)
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#define TRIGCON_SWTRIGEN (1 << 0)
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/* DECON_CRCCTRL */
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#define CRCCTRL_CRCCLKEN (0x1 << 2)
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#define CRCCTRL_CRCSTART_F (0x1 << 1)
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#define CRCCTRL_CRCEN (0x1 << 0)
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#define CRCCTRL_MASK (0x7)
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#endif /* EXYNOS_REGS_DECON_H */
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