mirror of
https://github.com/torvalds/linux.git
synced 2024-11-29 15:41:36 +00:00
1f7a04a0e6
In general it's a good idea to avoid using bare unreachable() because it
introduces undefined behavior in compiled code. but it caused a compilation warning,
Using BUG() instead of unreachable() to resolve compilation warnings.
Fixes the following warnings:
drivers/clk/sophgo/clk-cv18xx-ip.o: warning: objtool: mmux_round_rate() falls through to next function bypass_div_round_rate()
Fixes: 80fd61ec46 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Li Qiang <liqiang01@kylinos.cn>
Link: https://lore.kernel.org/r/c8e66d51f880127549e2a3e623be6787f62b310d.1720506143.git.liqiang01@kylinos.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
888 lines
21 KiB
C
888 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/gcd.h>
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#include <linux/spinlock.h>
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#include "clk-cv18xx-ip.h"
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/* GATE */
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static inline struct cv1800_clk_gate *hw_to_cv1800_clk_gate(struct clk_hw *hw)
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{
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struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
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return container_of(common, struct cv1800_clk_gate, common);
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}
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static int gate_enable(struct clk_hw *hw)
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{
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struct cv1800_clk_gate *gate = hw_to_cv1800_clk_gate(hw);
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return cv1800_clk_setbit(&gate->common, &gate->gate);
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}
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static void gate_disable(struct clk_hw *hw)
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{
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struct cv1800_clk_gate *gate = hw_to_cv1800_clk_gate(hw);
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cv1800_clk_clearbit(&gate->common, &gate->gate);
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}
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static int gate_is_enabled(struct clk_hw *hw)
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{
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struct cv1800_clk_gate *gate = hw_to_cv1800_clk_gate(hw);
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return cv1800_clk_checkbit(&gate->common, &gate->gate);
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}
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static unsigned long gate_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return parent_rate;
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}
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static long gate_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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return *parent_rate;
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}
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static int gate_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return 0;
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}
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const struct clk_ops cv1800_clk_gate_ops = {
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.disable = gate_disable,
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.enable = gate_enable,
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.is_enabled = gate_is_enabled,
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.recalc_rate = gate_recalc_rate,
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.round_rate = gate_round_rate,
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.set_rate = gate_set_rate,
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};
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/* DIV */
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#define _DIV_EN_CLK_DIV_FACTOR_FIELD BIT(3)
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#define DIV_GET_EN_CLK_DIV_FACTOR(_reg) \
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FIELD_GET(_DIV_EN_CLK_DIV_FACTOR_FIELD, _reg)
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#define DIV_SET_EN_DIV_FACTOR(_reg) \
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_CV1800_SET_FIELD(_reg, 1, _DIV_EN_CLK_DIV_FACTOR_FIELD)
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static inline struct cv1800_clk_div *hw_to_cv1800_clk_div(struct clk_hw *hw)
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{
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struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
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return container_of(common, struct cv1800_clk_div, common);
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}
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static int div_enable(struct clk_hw *hw)
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{
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struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
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return cv1800_clk_setbit(&div->common, &div->gate);
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}
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static void div_disable(struct clk_hw *hw)
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{
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struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
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cv1800_clk_clearbit(&div->common, &div->gate);
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}
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static int div_is_enabled(struct clk_hw *hw)
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{
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struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
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return cv1800_clk_checkbit(&div->common, &div->gate);
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}
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static int div_helper_set_rate(struct cv1800_clk_common *common,
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struct cv1800_clk_regfield *div,
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unsigned long val)
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{
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unsigned long flags;
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u32 reg;
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if (div->width == 0)
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return 0;
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spin_lock_irqsave(common->lock, flags);
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reg = readl(common->base + div->reg);
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reg = cv1800_clk_regfield_set(reg, val, div);
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if (div->initval > 0)
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reg = DIV_SET_EN_DIV_FACTOR(reg);
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writel(reg, common->base + div->reg);
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spin_unlock_irqrestore(common->lock, flags);
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return 0;
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}
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static u32 div_helper_get_clockdiv(struct cv1800_clk_common *common,
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struct cv1800_clk_regfield *div)
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{
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u32 clockdiv = 1;
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u32 reg;
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if (!div || div->initval < 0 || (div->width == 0 && div->initval <= 0))
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return 1;
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if (div->width == 0 && div->initval > 0)
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return div->initval;
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reg = readl(common->base + div->reg);
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if (div->initval == 0 || DIV_GET_EN_CLK_DIV_FACTOR(reg))
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clockdiv = cv1800_clk_regfield_get(reg, div);
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else if (div->initval > 0)
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clockdiv = div->initval;
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return clockdiv;
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}
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static u32 div_helper_round_rate(struct cv1800_clk_regfield *div,
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struct clk_hw *hw, struct clk_hw *parent,
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unsigned long rate, unsigned long *prate)
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{
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if (div->width == 0) {
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if (div->initval <= 0)
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return DIV_ROUND_UP_ULL(*prate, 1);
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else
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return DIV_ROUND_UP_ULL(*prate, div->initval);
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}
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return divider_round_rate_parent(hw, parent, rate, prate, NULL,
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div->width, div->flags);
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}
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static long div_round_rate(struct clk_hw *parent, unsigned long *parent_rate,
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unsigned long rate, int id, void *data)
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{
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struct cv1800_clk_div *div = data;
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return div_helper_round_rate(&div->div, &div->common.hw, parent,
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rate, parent_rate);
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}
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static bool div_is_better_rate(struct cv1800_clk_common *common,
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unsigned long target, unsigned long now,
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unsigned long best)
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{
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if (common->features & CLK_DIVIDER_ROUND_CLOSEST)
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return abs_diff(target, now) < abs_diff(target, best);
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return now <= target && now > best;
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}
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static int mux_helper_determine_rate(struct cv1800_clk_common *common,
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struct clk_rate_request *req,
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long (*round)(struct clk_hw *,
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unsigned long *,
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unsigned long,
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int,
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void *),
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void *data)
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{
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unsigned long best_parent_rate = 0, best_rate = 0;
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struct clk_hw *best_parent, *hw = &common->hw;
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unsigned int i;
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
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unsigned long adj_parent_rate;
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best_parent = clk_hw_get_parent(hw);
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best_parent_rate = clk_hw_get_rate(best_parent);
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best_rate = round(best_parent, &adj_parent_rate,
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req->rate, -1, data);
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goto find;
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}
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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unsigned long tmp_rate, parent_rate;
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struct clk_hw *parent;
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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parent_rate = clk_hw_get_rate(parent);
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tmp_rate = round(parent, &parent_rate, req->rate, i, data);
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if (tmp_rate == req->rate) {
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best_parent = parent;
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best_parent_rate = parent_rate;
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best_rate = tmp_rate;
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goto find;
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}
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if (div_is_better_rate(common, req->rate,
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tmp_rate, best_rate)) {
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best_parent = parent;
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best_parent_rate = parent_rate;
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best_rate = tmp_rate;
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}
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}
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if (best_rate == 0)
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return -EINVAL;
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find:
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req->best_parent_hw = best_parent;
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req->best_parent_rate = best_parent_rate;
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req->rate = best_rate;
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return 0;
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}
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static int div_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
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return mux_helper_determine_rate(&div->common, req,
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div_round_rate, div);
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}
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static unsigned long div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
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unsigned long val;
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val = div_helper_get_clockdiv(&div->common, &div->div);
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if (val == 0)
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return 0;
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return divider_recalc_rate(hw, parent_rate, val, NULL,
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div->div.flags, div->div.width);
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}
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static int div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
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unsigned long val;
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val = divider_get_val(rate, parent_rate, NULL,
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div->div.width, div->div.flags);
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return div_helper_set_rate(&div->common, &div->div, val);
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}
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const struct clk_ops cv1800_clk_div_ops = {
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.disable = div_disable,
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.enable = div_enable,
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.is_enabled = div_is_enabled,
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.determine_rate = div_determine_rate,
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.recalc_rate = div_recalc_rate,
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.set_rate = div_set_rate,
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};
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static inline struct cv1800_clk_bypass_div *
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hw_to_cv1800_clk_bypass_div(struct clk_hw *hw)
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{
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struct cv1800_clk_div *div = hw_to_cv1800_clk_div(hw);
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return container_of(div, struct cv1800_clk_bypass_div, div);
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}
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static long bypass_div_round_rate(struct clk_hw *parent,
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unsigned long *parent_rate,
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unsigned long rate, int id, void *data)
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{
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struct cv1800_clk_bypass_div *div = data;
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if (id == -1) {
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if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
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return *parent_rate;
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else
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return div_round_rate(parent, parent_rate, rate,
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-1, &div->div);
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}
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if (id == 0)
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return *parent_rate;
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return div_round_rate(parent, parent_rate, rate, id - 1, &div->div);
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}
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static int bypass_div_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
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return mux_helper_determine_rate(&div->div.common, req,
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bypass_div_round_rate, div);
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}
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static unsigned long bypass_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
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if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
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return parent_rate;
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return div_recalc_rate(hw, parent_rate);
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}
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static int bypass_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
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if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
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return 0;
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return div_set_rate(hw, rate, parent_rate);
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}
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static u8 bypass_div_get_parent(struct clk_hw *hw)
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{
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struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
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if (cv1800_clk_checkbit(&div->div.common, &div->bypass))
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return 0;
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return 1;
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}
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static int bypass_div_set_parent(struct clk_hw *hw, u8 index)
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{
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struct cv1800_clk_bypass_div *div = hw_to_cv1800_clk_bypass_div(hw);
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if (index)
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return cv1800_clk_clearbit(&div->div.common, &div->bypass);
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return cv1800_clk_setbit(&div->div.common, &div->bypass);
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}
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const struct clk_ops cv1800_clk_bypass_div_ops = {
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.disable = div_disable,
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.enable = div_enable,
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.is_enabled = div_is_enabled,
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.determine_rate = bypass_div_determine_rate,
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.recalc_rate = bypass_div_recalc_rate,
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.set_rate = bypass_div_set_rate,
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.set_parent = bypass_div_set_parent,
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.get_parent = bypass_div_get_parent,
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};
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/* MUX */
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static inline struct cv1800_clk_mux *hw_to_cv1800_clk_mux(struct clk_hw *hw)
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{
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struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
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return container_of(common, struct cv1800_clk_mux, common);
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}
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static int mux_enable(struct clk_hw *hw)
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{
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struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
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return cv1800_clk_setbit(&mux->common, &mux->gate);
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}
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static void mux_disable(struct clk_hw *hw)
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{
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struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
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cv1800_clk_clearbit(&mux->common, &mux->gate);
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}
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static int mux_is_enabled(struct clk_hw *hw)
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{
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struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
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return cv1800_clk_checkbit(&mux->common, &mux->gate);
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}
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static long mux_round_rate(struct clk_hw *parent, unsigned long *parent_rate,
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unsigned long rate, int id, void *data)
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{
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struct cv1800_clk_mux *mux = data;
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return div_helper_round_rate(&mux->div, &mux->common.hw, parent,
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rate, parent_rate);
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}
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static int mux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
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return mux_helper_determine_rate(&mux->common, req,
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mux_round_rate, mux);
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}
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static unsigned long mux_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
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unsigned long val;
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val = div_helper_get_clockdiv(&mux->common, &mux->div);
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if (val == 0)
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return 0;
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return divider_recalc_rate(hw, parent_rate, val, NULL,
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mux->div.flags, mux->div.width);
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}
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static int mux_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
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unsigned long val;
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val = divider_get_val(rate, parent_rate, NULL,
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mux->div.width, mux->div.flags);
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return div_helper_set_rate(&mux->common, &mux->div, val);
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}
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static u8 mux_get_parent(struct clk_hw *hw)
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{
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struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
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u32 reg = readl(mux->common.base + mux->mux.reg);
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return cv1800_clk_regfield_get(reg, &mux->mux);
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}
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static int _mux_set_parent(struct cv1800_clk_mux *mux, u8 index)
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{
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u32 reg;
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reg = readl(mux->common.base + mux->mux.reg);
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reg = cv1800_clk_regfield_set(reg, index, &mux->mux);
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writel(reg, mux->common.base + mux->mux.reg);
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return 0;
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}
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static int mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
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unsigned long flags;
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spin_lock_irqsave(mux->common.lock, flags);
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_mux_set_parent(mux, index);
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spin_unlock_irqrestore(mux->common.lock, flags);
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return 0;
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}
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const struct clk_ops cv1800_clk_mux_ops = {
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.disable = mux_disable,
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.enable = mux_enable,
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.is_enabled = mux_is_enabled,
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.determine_rate = mux_determine_rate,
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.recalc_rate = mux_recalc_rate,
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.set_rate = mux_set_rate,
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.set_parent = mux_set_parent,
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.get_parent = mux_get_parent,
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};
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static inline struct cv1800_clk_bypass_mux *
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hw_to_cv1800_clk_bypass_mux(struct clk_hw *hw)
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{
|
|
struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw);
|
|
|
|
return container_of(mux, struct cv1800_clk_bypass_mux, mux);
|
|
}
|
|
|
|
static long bypass_mux_round_rate(struct clk_hw *parent,
|
|
unsigned long *parent_rate,
|
|
unsigned long rate, int id, void *data)
|
|
{
|
|
struct cv1800_clk_bypass_mux *mux = data;
|
|
|
|
if (id == -1) {
|
|
if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass))
|
|
return *parent_rate;
|
|
else
|
|
return mux_round_rate(parent, parent_rate, rate,
|
|
-1, &mux->mux);
|
|
}
|
|
|
|
if (id == 0)
|
|
return *parent_rate;
|
|
|
|
return mux_round_rate(parent, parent_rate, rate, id - 1, &mux->mux);
|
|
}
|
|
|
|
static int bypass_mux_determine_rate(struct clk_hw *hw,
|
|
struct clk_rate_request *req)
|
|
{
|
|
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
|
|
|
|
return mux_helper_determine_rate(&mux->mux.common, req,
|
|
bypass_mux_round_rate, mux);
|
|
}
|
|
|
|
static unsigned long bypass_mux_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
|
|
|
|
if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass))
|
|
return parent_rate;
|
|
|
|
return mux_recalc_rate(hw, parent_rate);
|
|
}
|
|
|
|
static int bypass_mux_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
|
|
|
|
if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass))
|
|
return 0;
|
|
|
|
return mux_set_rate(hw, rate, parent_rate);
|
|
}
|
|
|
|
static u8 bypass_mux_get_parent(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
|
|
|
|
if (cv1800_clk_checkbit(&mux->mux.common, &mux->bypass))
|
|
return 0;
|
|
|
|
return mux_get_parent(hw) + 1;
|
|
}
|
|
|
|
static int bypass_mux_set_parent(struct clk_hw *hw, u8 index)
|
|
{
|
|
struct cv1800_clk_bypass_mux *mux = hw_to_cv1800_clk_bypass_mux(hw);
|
|
|
|
if (index == 0)
|
|
return cv1800_clk_setbit(&mux->mux.common, &mux->bypass);
|
|
|
|
return cv1800_clk_clearbit(&mux->mux.common, &mux->bypass);
|
|
}
|
|
|
|
const struct clk_ops cv1800_clk_bypass_mux_ops = {
|
|
.disable = mux_disable,
|
|
.enable = mux_enable,
|
|
.is_enabled = mux_is_enabled,
|
|
|
|
.determine_rate = bypass_mux_determine_rate,
|
|
.recalc_rate = bypass_mux_recalc_rate,
|
|
.set_rate = bypass_mux_set_rate,
|
|
|
|
.set_parent = bypass_mux_set_parent,
|
|
.get_parent = bypass_mux_get_parent,
|
|
};
|
|
|
|
/* MMUX */
|
|
static inline struct cv1800_clk_mmux *hw_to_cv1800_clk_mmux(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
|
|
|
|
return container_of(common, struct cv1800_clk_mmux, common);
|
|
}
|
|
|
|
static u8 mmux_get_parent_id(struct cv1800_clk_mmux *mmux)
|
|
{
|
|
struct clk_hw *hw = &mmux->common.hw;
|
|
struct clk_hw *parent = clk_hw_get_parent(hw);
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
|
|
if (parent == clk_hw_get_parent_by_index(hw, i))
|
|
return i;
|
|
}
|
|
|
|
BUG();
|
|
}
|
|
|
|
static int mmux_enable(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
|
|
|
|
return cv1800_clk_setbit(&mmux->common, &mmux->gate);
|
|
}
|
|
|
|
static void mmux_disable(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
|
|
|
|
cv1800_clk_clearbit(&mmux->common, &mmux->gate);
|
|
}
|
|
|
|
static int mmux_is_enabled(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
|
|
|
|
return cv1800_clk_checkbit(&mmux->common, &mmux->gate);
|
|
}
|
|
|
|
static long mmux_round_rate(struct clk_hw *parent, unsigned long *parent_rate,
|
|
unsigned long rate, int id, void *data)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = data;
|
|
s8 div_id;
|
|
|
|
if (id == -1) {
|
|
if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
|
|
return *parent_rate;
|
|
|
|
id = mmux_get_parent_id(mmux);
|
|
}
|
|
|
|
div_id = mmux->parent2sel[id];
|
|
|
|
if (div_id < 0)
|
|
return *parent_rate;
|
|
|
|
return div_helper_round_rate(&mmux->div[div_id],
|
|
&mmux->common.hw, parent,
|
|
rate, parent_rate);
|
|
}
|
|
|
|
static int mmux_determine_rate(struct clk_hw *hw,
|
|
struct clk_rate_request *req)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
|
|
|
|
return mux_helper_determine_rate(&mmux->common, req,
|
|
mmux_round_rate, mmux);
|
|
}
|
|
|
|
static unsigned long mmux_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
|
|
unsigned long val;
|
|
struct cv1800_clk_regfield *div;
|
|
|
|
if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
|
|
return parent_rate;
|
|
|
|
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
|
|
div = &mmux->div[0];
|
|
else
|
|
div = &mmux->div[1];
|
|
|
|
val = div_helper_get_clockdiv(&mmux->common, div);
|
|
if (val == 0)
|
|
return 0;
|
|
|
|
return divider_recalc_rate(hw, parent_rate, val, NULL,
|
|
div->flags, div->width);
|
|
}
|
|
|
|
static int mmux_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
|
|
struct cv1800_clk_regfield *div;
|
|
unsigned long val;
|
|
|
|
if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
|
|
return parent_rate;
|
|
|
|
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
|
|
div = &mmux->div[0];
|
|
else
|
|
div = &mmux->div[1];
|
|
|
|
val = divider_get_val(rate, parent_rate, NULL,
|
|
div->width, div->flags);
|
|
|
|
return div_helper_set_rate(&mmux->common, div, val);
|
|
}
|
|
|
|
static u8 mmux_get_parent(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
|
|
struct cv1800_clk_regfield *mux;
|
|
u32 reg;
|
|
s8 clk_sel;
|
|
|
|
if (cv1800_clk_checkbit(&mmux->common, &mmux->bypass))
|
|
return 0;
|
|
|
|
if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel))
|
|
clk_sel = 0;
|
|
else
|
|
clk_sel = 1;
|
|
mux = &mmux->mux[clk_sel];
|
|
|
|
reg = readl(mmux->common.base + mux->reg);
|
|
|
|
return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)];
|
|
}
|
|
|
|
static int mmux_set_parent(struct clk_hw *hw, u8 index)
|
|
{
|
|
struct cv1800_clk_mmux *mmux = hw_to_cv1800_clk_mmux(hw);
|
|
struct cv1800_clk_regfield *mux;
|
|
unsigned long flags;
|
|
u32 reg;
|
|
s8 clk_sel = mmux->parent2sel[index];
|
|
|
|
if (index == 0 || clk_sel == -1) {
|
|
cv1800_clk_setbit(&mmux->common, &mmux->bypass);
|
|
goto release;
|
|
}
|
|
|
|
cv1800_clk_clearbit(&mmux->common, &mmux->bypass);
|
|
|
|
if (clk_sel)
|
|
cv1800_clk_clearbit(&mmux->common, &mmux->clk_sel);
|
|
else
|
|
cv1800_clk_setbit(&mmux->common, &mmux->clk_sel);
|
|
|
|
spin_lock_irqsave(mmux->common.lock, flags);
|
|
|
|
mux = &mmux->mux[clk_sel];
|
|
reg = readl(mmux->common.base + mux->reg);
|
|
reg = cv1800_clk_regfield_set(reg, index, mux);
|
|
|
|
writel(reg, mmux->common.base + mux->reg);
|
|
|
|
spin_unlock_irqrestore(mmux->common.lock, flags);
|
|
|
|
release:
|
|
return 0;
|
|
}
|
|
|
|
const struct clk_ops cv1800_clk_mmux_ops = {
|
|
.disable = mmux_disable,
|
|
.enable = mmux_enable,
|
|
.is_enabled = mmux_is_enabled,
|
|
|
|
.determine_rate = mmux_determine_rate,
|
|
.recalc_rate = mmux_recalc_rate,
|
|
.set_rate = mmux_set_rate,
|
|
|
|
.set_parent = mmux_set_parent,
|
|
.get_parent = mmux_get_parent,
|
|
};
|
|
|
|
/* AUDIO CLK */
|
|
static inline struct cv1800_clk_audio *
|
|
hw_to_cv1800_clk_audio(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_common *common = hw_to_cv1800_clk_common(hw);
|
|
|
|
return container_of(common, struct cv1800_clk_audio, common);
|
|
}
|
|
|
|
static int aclk_enable(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
|
|
|
|
cv1800_clk_setbit(&aclk->common, &aclk->src_en);
|
|
return cv1800_clk_setbit(&aclk->common, &aclk->output_en);
|
|
}
|
|
|
|
static void aclk_disable(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
|
|
|
|
cv1800_clk_clearbit(&aclk->common, &aclk->output_en);
|
|
cv1800_clk_clearbit(&aclk->common, &aclk->src_en);
|
|
}
|
|
|
|
static int aclk_is_enabled(struct clk_hw *hw)
|
|
{
|
|
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
|
|
|
|
return cv1800_clk_checkbit(&aclk->common, &aclk->output_en);
|
|
}
|
|
|
|
static int aclk_determine_rate(struct clk_hw *hw,
|
|
struct clk_rate_request *req)
|
|
{
|
|
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
|
|
|
|
req->rate = aclk->target_rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long aclk_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
|
|
u64 rate = parent_rate;
|
|
u64 factor = 2;
|
|
u32 regval;
|
|
|
|
if (!cv1800_clk_checkbit(&aclk->common, &aclk->div_en))
|
|
return 0;
|
|
|
|
regval = readl(aclk->common.base + aclk->m.reg);
|
|
factor *= cv1800_clk_regfield_get(regval, &aclk->m);
|
|
|
|
regval = readl(aclk->common.base + aclk->n.reg);
|
|
rate *= cv1800_clk_regfield_get(regval, &aclk->n);
|
|
|
|
return DIV64_U64_ROUND_UP(rate, factor);
|
|
}
|
|
|
|
static void aclk_determine_mn(unsigned long parent_rate, unsigned long rate,
|
|
u32 *m, u32 *n)
|
|
{
|
|
u32 tm = parent_rate / 2;
|
|
u32 tn = rate;
|
|
u32 tcommon = gcd(tm, tn);
|
|
*m = tm / tcommon;
|
|
*n = tn / tcommon;
|
|
}
|
|
|
|
static int aclk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct cv1800_clk_audio *aclk = hw_to_cv1800_clk_audio(hw);
|
|
unsigned long flags;
|
|
u32 m, n;
|
|
|
|
aclk_determine_mn(parent_rate, rate,
|
|
&m, &n);
|
|
|
|
spin_lock_irqsave(aclk->common.lock, flags);
|
|
|
|
writel(m, aclk->common.base + aclk->m.reg);
|
|
writel(n, aclk->common.base + aclk->n.reg);
|
|
|
|
cv1800_clk_setbit(&aclk->common, &aclk->div_en);
|
|
cv1800_clk_setbit(&aclk->common, &aclk->div_up);
|
|
|
|
spin_unlock_irqrestore(aclk->common.lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct clk_ops cv1800_clk_audio_ops = {
|
|
.disable = aclk_disable,
|
|
.enable = aclk_enable,
|
|
.is_enabled = aclk_is_enabled,
|
|
|
|
.determine_rate = aclk_determine_rate,
|
|
.recalc_rate = aclk_recalc_rate,
|
|
.set_rate = aclk_set_rate,
|
|
};
|