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The simpler AT91x40 processors do not have the same power management controller as the new AT91 devices. They do have a simpler power controller module that we can use to disable the CPU clock at idle time. Add code to support that. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
62 lines
2.2 KiB
C
62 lines
2.2 KiB
C
/*
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* arch/arm/mach-at91/include/mach/at91x40.h
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*
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* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91X40_H
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#define AT91X40_H
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/*
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* IRQ list.
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*/
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#define AT91_ID_FIQ 0 /* FIQ */
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#define AT91_ID_SYS 1 /* System Peripheral */
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#define AT91X40_ID_USART0 2 /* USART port 0 */
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#define AT91X40_ID_USART1 3 /* USART port 1 */
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#define AT91X40_ID_TC0 4 /* Timer/Counter 0 */
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#define AT91X40_ID_TC1 5 /* Timer/Counter 1*/
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#define AT91X40_ID_TC2 6 /* Timer/Counter 2*/
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#define AT91X40_ID_WD 7 /* Watchdog? */
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#define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */
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#define AT91X40_ID_IRQ0 16 /* External IRQ 0 */
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#define AT91X40_ID_IRQ1 17 /* External IRQ 1 */
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#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
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/*
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* System Peripherals (offset from AT91_BASE_SYS)
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*/
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#define AT91_BASE_SYS 0xffc00000
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#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */
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#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */
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#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */
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#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */
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#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */
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#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */
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#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */
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#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */
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#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
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/*
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* The AT91x40 series doesn't have a debug unit like the other AT91 parts.
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* But it does have a chip identify register and extension ID, so define at
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* least these here.
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*/
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#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
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#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
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/*
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* Support defines for the simple Power Controller module.
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*/
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#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
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#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
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#endif /* AT91X40_H */
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