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b340cacc1b
My philosophy is unused code is dead code. And dead code is subject to bit
rot and is a likely source of bugs. Use it or lose it.
This reverts parts of c320b976d7 ("PCI: Add implementation for PRI
capability"), removing these interfaces:
pci_pri_enabled()
pci_pri_stopped()
pci_pri_status()
[bhelgaas: split to separate patch]
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: Joerg Roedel <joro@8bytes.org>
376 lines
8.6 KiB
C
376 lines
8.6 KiB
C
/*
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* drivers/pci/ats.c
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*
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* Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
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* Copyright (C) 2011 Advanced Micro Devices,
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*
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* PCI Express I/O Virtualization (IOV) support.
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* Address Translation Service 1.0
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* Page Request Interface added by Joerg Roedel <joerg.roedel@amd.com>
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* PASID support added by Joerg Roedel <joerg.roedel@amd.com>
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*/
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#include <linux/export.h>
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#include <linux/pci-ats.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include "pci.h"
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static int ats_alloc_one(struct pci_dev *dev, int ps)
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{
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int pos;
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u16 cap;
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struct pci_ats *ats;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
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if (!pos)
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return -ENODEV;
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ats = kzalloc(sizeof(*ats), GFP_KERNEL);
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if (!ats)
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return -ENOMEM;
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ats->pos = pos;
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ats->stu = ps;
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pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
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ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
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PCI_ATS_MAX_QDEP;
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dev->ats = ats;
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return 0;
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}
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static void ats_free_one(struct pci_dev *dev)
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{
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kfree(dev->ats);
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dev->ats = NULL;
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}
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/**
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* pci_enable_ats - enable the ATS capability
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* @dev: the PCI device
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* @ps: the IOMMU page shift
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*
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* Returns 0 on success, or negative on failure.
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*/
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int pci_enable_ats(struct pci_dev *dev, int ps)
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{
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int rc;
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u16 ctrl;
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BUG_ON(dev->ats && dev->ats->is_enabled);
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if (ps < PCI_ATS_MIN_STU)
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return -EINVAL;
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if (dev->is_physfn || dev->is_virtfn) {
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struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
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mutex_lock(&pdev->sriov->lock);
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if (pdev->ats)
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rc = pdev->ats->stu == ps ? 0 : -EINVAL;
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else
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rc = ats_alloc_one(pdev, ps);
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if (!rc)
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pdev->ats->ref_cnt++;
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mutex_unlock(&pdev->sriov->lock);
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if (rc)
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return rc;
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}
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if (!dev->is_physfn) {
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rc = ats_alloc_one(dev, ps);
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if (rc)
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return rc;
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}
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ctrl = PCI_ATS_CTRL_ENABLE;
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if (!dev->is_virtfn)
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ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
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pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
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dev->ats->is_enabled = 1;
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_enable_ats);
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/**
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* pci_disable_ats - disable the ATS capability
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* @dev: the PCI device
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*/
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void pci_disable_ats(struct pci_dev *dev)
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{
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u16 ctrl;
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BUG_ON(!dev->ats || !dev->ats->is_enabled);
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pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl);
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ctrl &= ~PCI_ATS_CTRL_ENABLE;
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pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
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dev->ats->is_enabled = 0;
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if (dev->is_physfn || dev->is_virtfn) {
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struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
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mutex_lock(&pdev->sriov->lock);
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pdev->ats->ref_cnt--;
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if (!pdev->ats->ref_cnt)
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ats_free_one(pdev);
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mutex_unlock(&pdev->sriov->lock);
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}
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if (!dev->is_physfn)
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ats_free_one(dev);
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}
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EXPORT_SYMBOL_GPL(pci_disable_ats);
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void pci_restore_ats_state(struct pci_dev *dev)
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{
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u16 ctrl;
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if (!pci_ats_enabled(dev))
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return;
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if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS))
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BUG();
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ctrl = PCI_ATS_CTRL_ENABLE;
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if (!dev->is_virtfn)
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ctrl |= PCI_ATS_CTRL_STU(dev->ats->stu - PCI_ATS_MIN_STU);
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pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
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}
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EXPORT_SYMBOL_GPL(pci_restore_ats_state);
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/**
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* pci_ats_queue_depth - query the ATS Invalidate Queue Depth
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* @dev: the PCI device
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*
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* Returns the queue depth on success, or negative on failure.
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*
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* The ATS spec uses 0 in the Invalidate Queue Depth field to
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* indicate that the function can accept 32 Invalidate Request.
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* But here we use the `real' values (i.e. 1~32) for the Queue
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* Depth; and 0 indicates the function shares the Queue with
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* other functions (doesn't exclusively own a Queue).
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*/
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int pci_ats_queue_depth(struct pci_dev *dev)
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{
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int pos;
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u16 cap;
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if (dev->is_virtfn)
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return 0;
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if (dev->ats)
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return dev->ats->qdep;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
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if (!pos)
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return -ENODEV;
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pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
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return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
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PCI_ATS_MAX_QDEP;
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}
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EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
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#ifdef CONFIG_PCI_PRI
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/**
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* pci_enable_pri - Enable PRI capability
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* @ pdev: PCI device structure
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*
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* Returns 0 on success, negative value on error
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*/
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int pci_enable_pri(struct pci_dev *pdev, u32 reqs)
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{
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u16 control, status;
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u32 max_requests;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
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pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
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if ((control & PCI_PRI_CTRL_ENABLE) ||
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!(status & PCI_PRI_STATUS_STOPPED))
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return -EBUSY;
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pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
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reqs = min(max_requests, reqs);
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pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);
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control |= PCI_PRI_CTRL_ENABLE;
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pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_enable_pri);
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/**
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* pci_disable_pri - Disable PRI capability
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* @pdev: PCI device structure
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*
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* Only clears the enabled-bit, regardless of its former value
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*/
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void pci_disable_pri(struct pci_dev *pdev)
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{
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u16 control;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return;
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pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
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control &= ~PCI_PRI_CTRL_ENABLE;
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pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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}
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EXPORT_SYMBOL_GPL(pci_disable_pri);
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/**
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* pci_reset_pri - Resets device's PRI state
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* @pdev: PCI device structure
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*
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* The PRI capability must be disabled before this function is called.
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* Returns 0 on success, negative value on error.
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*/
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int pci_reset_pri(struct pci_dev *pdev)
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{
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u16 control;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
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if (control & PCI_PRI_CTRL_ENABLE)
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return -EBUSY;
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control |= PCI_PRI_CTRL_RESET;
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pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_reset_pri);
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#endif /* CONFIG_PCI_PRI */
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#ifdef CONFIG_PCI_PASID
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/**
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* pci_enable_pasid - Enable the PASID capability
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* @pdev: PCI device structure
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* @features: Features to enable
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*
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* Returns 0 on success, negative value on error. This function checks
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* whether the features are actually supported by the device and returns
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* an error if not.
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*/
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int pci_enable_pasid(struct pci_dev *pdev, int features)
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{
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u16 control, supported;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CTRL, &control);
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pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
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if (control & PCI_PASID_CTRL_ENABLE)
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return -EINVAL;
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supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
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/* User wants to enable anything unsupported? */
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if ((supported & features) != features)
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return -EINVAL;
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control = PCI_PASID_CTRL_ENABLE | features;
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pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pci_enable_pasid);
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/**
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* pci_disable_pasid - Disable the PASID capability
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* @pdev: PCI device structure
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*
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*/
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void pci_disable_pasid(struct pci_dev *pdev)
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{
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u16 control = 0;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return;
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pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);
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}
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EXPORT_SYMBOL_GPL(pci_disable_pasid);
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/**
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* pci_pasid_features - Check which PASID features are supported
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* @pdev: PCI device structure
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*
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* Returns a negative value when no PASI capability is present.
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* Otherwise is returns a bitmask with supported features. Current
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* features reported are:
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* PCI_PASID_CAP_EXEC - Execute permission supported
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* PCI_PASID_CAP_PRIV - Privileged mode supported
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*/
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int pci_pasid_features(struct pci_dev *pdev)
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{
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u16 supported;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
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supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;
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return supported;
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}
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EXPORT_SYMBOL_GPL(pci_pasid_features);
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#define PASID_NUMBER_SHIFT 8
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#define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT)
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/**
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* pci_max_pasid - Get maximum number of PASIDs supported by device
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* @pdev: PCI device structure
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*
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* Returns negative value when PASID capability is not present.
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* Otherwise it returns the numer of supported PASIDs.
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*/
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int pci_max_pasids(struct pci_dev *pdev)
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{
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u16 supported;
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int pos;
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pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
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if (!pos)
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return -EINVAL;
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pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);
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supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;
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return (1 << supported);
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}
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EXPORT_SYMBOL_GPL(pci_max_pasids);
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#endif /* CONFIG_PCI_PASID */
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