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8ddad55899
Fix the issue where MEM_TO_MEM fail on i.MX8QM due to the requirement
that both source and destination addresses need pass through the IOMMU.
Typically, peripheral FIFO addresses bypass the IOMMU, necessitating
only one of the source or destination to go through it.
Set "is_remote" to true to ensure both source and destination
addresses pass through the IOMMU.
iMX8 Spec define "Local" and "Remote" bus as below.
Local bus: bypass IOMMU to directly access other peripheral register,
such as FIFO.
Remote bus: go through IOMMU to access system memory.
The test fail log as follow:
[ 66.268506] dmatest: dma0chan0-copy0: result #1: 'test timed out' with src_off=0x100 dst_off=0x80 len=0x3ec0 (0)
[ 66.278785] dmatest: dma0chan0-copy0: summary 1 tests, 1 failures 0.32 iops 4 KB/s (0)
Fixes: 72f5801a4e ("dmaengine: fsl-edma: integrate v3 support")
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Cc: stable@vger.kernel.org
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240510030959.703663-1-joy.zou@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
492 lines
14 KiB
C
492 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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* Copyright 2018 Angelo Dureghello <angelo@sysam.it>
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*/
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#ifndef _FSL_EDMA_COMMON_H_
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#define _FSL_EDMA_COMMON_H_
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#include <linux/dma-direction.h>
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#include <linux/platform_device.h>
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#include "virt-dma.h"
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#define EDMA_CR_EDBG BIT(1)
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#define EDMA_CR_ERCA BIT(2)
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#define EDMA_CR_ERGA BIT(3)
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#define EDMA_CR_HOE BIT(4)
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#define EDMA_CR_HALT BIT(5)
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#define EDMA_CR_CLM BIT(6)
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#define EDMA_CR_EMLM BIT(7)
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#define EDMA_CR_ECX BIT(16)
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#define EDMA_CR_CX BIT(17)
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#define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0))
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#define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0))
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#define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))
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#define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))
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#define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))
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#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
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#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
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#define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11)
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#define EDMA_TCD_ITER_MASK GENMASK(14, 0)
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#define EDMA_TCD_CITER_CITER(x) ((x) & EDMA_TCD_ITER_MASK)
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#define EDMA_TCD_BITER_BITER(x) ((x) & EDMA_TCD_ITER_MASK)
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#define EDMA_TCD_CSR_START BIT(0)
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#define EDMA_TCD_CSR_INT_MAJOR BIT(1)
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#define EDMA_TCD_CSR_INT_HALF BIT(2)
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#define EDMA_TCD_CSR_D_REQ BIT(3)
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#define EDMA_TCD_CSR_E_SG BIT(4)
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#define EDMA_TCD_CSR_E_LINK BIT(5)
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#define EDMA_TCD_CSR_ACTIVE BIT(6)
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#define EDMA_TCD_CSR_DONE BIT(7)
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#define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0))
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#define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10)
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#define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30)
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#define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31)
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#define EDMAMUX_CHCFG_DIS 0x0
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#define EDMAMUX_CHCFG_ENBL 0x80
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#define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F)
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#define DMAMUX_NR 2
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#define EDMA_TCD 0x1000
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#define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
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#define EDMA_V3_CH_SBR_RD BIT(22)
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#define EDMA_V3_CH_SBR_WR BIT(21)
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#define EDMA_V3_CH_CSR_ERQ BIT(0)
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#define EDMA_V3_CH_CSR_EARQ BIT(1)
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#define EDMA_V3_CH_CSR_EEI BIT(2)
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#define EDMA_V3_CH_CSR_DONE BIT(30)
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#define EDMA_V3_CH_CSR_ACTIVE BIT(31)
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enum fsl_edma_pm_state {
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RUNNING = 0,
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SUSPENDED,
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};
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struct fsl_edma_hw_tcd {
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__le32 saddr;
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__le16 soff;
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__le16 attr;
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__le32 nbytes;
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__le32 slast;
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__le32 daddr;
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__le16 doff;
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__le16 citer;
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__le32 dlast_sga;
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__le16 csr;
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__le16 biter;
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};
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struct fsl_edma_hw_tcd64 {
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__le64 saddr;
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__le16 soff;
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__le16 attr;
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__le32 nbytes;
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__le64 slast;
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__le64 daddr;
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__le64 dlast_sga;
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__le16 doff;
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__le16 citer;
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__le16 csr;
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__le16 biter;
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} __packed;
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struct fsl_edma3_ch_reg {
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__le32 ch_csr;
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__le32 ch_es;
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__le32 ch_int;
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__le32 ch_sbr;
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__le32 ch_pri;
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__le32 ch_mux;
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__le32 ch_mattr; /* edma4, reserved for edma3 */
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__le32 ch_reserved;
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union {
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struct fsl_edma_hw_tcd tcd;
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struct fsl_edma_hw_tcd64 tcd64;
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};
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} __packed;
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/*
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* These are iomem pointers, for both v32 and v64.
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*/
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struct edma_regs {
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void __iomem *cr;
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void __iomem *es;
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void __iomem *erqh;
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void __iomem *erql; /* aka erq on v32 */
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void __iomem *eeih;
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void __iomem *eeil; /* aka eei on v32 */
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void __iomem *seei;
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void __iomem *ceei;
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void __iomem *serq;
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void __iomem *cerq;
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void __iomem *cint;
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void __iomem *cerr;
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void __iomem *ssrt;
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void __iomem *cdne;
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void __iomem *inth;
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void __iomem *intl;
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void __iomem *errh;
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void __iomem *errl;
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};
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struct fsl_edma_sw_tcd {
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dma_addr_t ptcd;
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void *vtcd;
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};
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struct fsl_edma_chan {
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struct virt_dma_chan vchan;
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enum dma_status status;
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enum fsl_edma_pm_state pm_state;
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struct fsl_edma_engine *edma;
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struct fsl_edma_desc *edesc;
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struct dma_slave_config cfg;
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u32 attr;
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bool is_sw;
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struct dma_pool *tcd_pool;
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dma_addr_t dma_dev_addr;
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u32 dma_dev_size;
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enum dma_data_direction dma_dir;
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char chan_name[32];
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void __iomem *tcd;
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void __iomem *mux_addr;
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u32 real_count;
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struct work_struct issue_worker;
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struct platform_device *pdev;
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struct device *pd_dev;
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u32 srcid;
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struct clk *clk;
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int priority;
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int hw_chanid;
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int txirq;
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irqreturn_t (*irq_handler)(int irq, void *dev_id);
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bool is_rxchan;
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bool is_remote;
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bool is_multi_fifo;
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};
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struct fsl_edma_desc {
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struct virt_dma_desc vdesc;
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struct fsl_edma_chan *echan;
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bool iscyclic;
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enum dma_transfer_direction dirn;
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unsigned int n_tcds;
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struct fsl_edma_sw_tcd tcd[];
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};
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#define FSL_EDMA_DRV_HAS_DMACLK BIT(0)
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#define FSL_EDMA_DRV_MUX_SWAP BIT(1)
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#define FSL_EDMA_DRV_CONFIG32 BIT(2)
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#define FSL_EDMA_DRV_WRAP_IO BIT(3)
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#define FSL_EDMA_DRV_EDMA64 BIT(4)
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#define FSL_EDMA_DRV_HAS_PD BIT(5)
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#define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
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#define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
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#define FSL_EDMA_DRV_MEM_REMOTE BIT(8)
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/* control and status register is in tcd address space, edma3 reg layout */
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#define FSL_EDMA_DRV_SPLIT_REG BIT(9)
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#define FSL_EDMA_DRV_BUS_8BYTE BIT(10)
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#define FSL_EDMA_DRV_DEV_TO_DEV BIT(11)
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#define FSL_EDMA_DRV_ALIGN_64BYTE BIT(12)
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/* Need clean CHn_CSR DONE before enable TCD's ESG */
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#define FSL_EDMA_DRV_CLEAR_DONE_E_SG BIT(13)
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/* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */
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#define FSL_EDMA_DRV_CLEAR_DONE_E_LINK BIT(14)
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#define FSL_EDMA_DRV_TCD64 BIT(15)
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#define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \
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FSL_EDMA_DRV_BUS_8BYTE | \
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FSL_EDMA_DRV_DEV_TO_DEV | \
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FSL_EDMA_DRV_ALIGN_64BYTE | \
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FSL_EDMA_DRV_CLEAR_DONE_E_SG | \
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FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
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#define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_SPLIT_REG | \
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FSL_EDMA_DRV_BUS_8BYTE | \
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FSL_EDMA_DRV_DEV_TO_DEV | \
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FSL_EDMA_DRV_ALIGN_64BYTE | \
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FSL_EDMA_DRV_CLEAR_DONE_E_LINK)
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struct fsl_edma_drvdata {
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u32 dmamuxs; /* only used before v3 */
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u32 chreg_off;
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u32 chreg_space_sz;
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u32 flags;
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u32 mux_off; /* channel mux register offset */
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u32 mux_skip; /* how much skip for each channel */
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int (*setup_irq)(struct platform_device *pdev,
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struct fsl_edma_engine *fsl_edma);
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};
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struct fsl_edma_engine {
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struct dma_device dma_dev;
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void __iomem *membase;
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void __iomem *muxbase[DMAMUX_NR];
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struct clk *muxclk[DMAMUX_NR];
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struct clk *dmaclk;
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struct mutex fsl_edma_mutex;
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const struct fsl_edma_drvdata *drvdata;
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u32 n_chans;
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int txirq;
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int errirq;
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bool big_endian;
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struct edma_regs regs;
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u64 chan_masked;
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struct fsl_edma_chan chans[] __counted_by(n_chans);
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};
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static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan)
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{
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return fsl_chan->edma->drvdata->flags;
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}
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#define edma_read_tcdreg_c(chan, _tcd, __name) \
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_Generic(((_tcd)->__name), \
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__iomem __le64 : edma_readq(chan->edma, &(_tcd)->__name), \
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__iomem __le32 : edma_readl(chan->edma, &(_tcd)->__name), \
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__iomem __le16 : edma_readw(chan->edma, &(_tcd)->__name) \
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)
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#define edma_read_tcdreg(chan, __name) \
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((fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) ? \
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edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd64 __iomem *)chan->tcd), __name) : \
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edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd __iomem *)chan->tcd), __name) \
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)
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#define edma_write_tcdreg_c(chan, _tcd, _val, __name) \
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_Generic((_tcd->__name), \
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__iomem __le64 : edma_writeq(chan->edma, (u64 __force)(_val), &_tcd->__name), \
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__iomem __le32 : edma_writel(chan->edma, (u32 __force)(_val), &_tcd->__name), \
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__iomem __le16 : edma_writew(chan->edma, (u16 __force)(_val), &_tcd->__name), \
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__iomem u8 : edma_writeb(chan->edma, _val, &_tcd->__name) \
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)
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#define edma_write_tcdreg(chan, val, __name) \
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do { \
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struct fsl_edma_hw_tcd64 __iomem *tcd64_r = (struct fsl_edma_hw_tcd64 __iomem *)chan->tcd; \
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struct fsl_edma_hw_tcd __iomem *tcd_r = (struct fsl_edma_hw_tcd __iomem *)chan->tcd; \
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\
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if (fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) \
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edma_write_tcdreg_c(chan, tcd64_r, val, __name); \
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else \
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edma_write_tcdreg_c(chan, tcd_r, val, __name); \
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} while (0)
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#define edma_cp_tcd_to_reg(chan, __tcd, __name) \
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do { \
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struct fsl_edma_hw_tcd64 __iomem *tcd64_r = (struct fsl_edma_hw_tcd64 __iomem *)chan->tcd; \
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struct fsl_edma_hw_tcd __iomem *tcd_r = (struct fsl_edma_hw_tcd __iomem *)chan->tcd; \
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struct fsl_edma_hw_tcd64 *tcd64_m = (struct fsl_edma_hw_tcd64 *)__tcd; \
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struct fsl_edma_hw_tcd *tcd_m = (struct fsl_edma_hw_tcd *)__tcd; \
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\
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if (fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) \
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edma_write_tcdreg_c(chan, tcd64_r, tcd64_m->__name, __name); \
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else \
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edma_write_tcdreg_c(chan, tcd_r, tcd_m->__name, __name); \
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} while (0)
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#define edma_readl_chreg(chan, __name) \
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edma_readl(chan->edma, \
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(void __iomem *)&(container_of(((__force void *)chan->tcd),\
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struct fsl_edma3_ch_reg, tcd)->__name))
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#define edma_writel_chreg(chan, val, __name) \
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edma_writel(chan->edma, val, \
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(void __iomem *)&(container_of(((__force void *)chan->tcd),\
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struct fsl_edma3_ch_reg, tcd)->__name))
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#define fsl_edma_get_tcd(_chan, _tcd, _field) \
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(fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
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(((struct fsl_edma_hw_tcd *)_tcd)->_field))
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#define fsl_edma_le_to_cpu(x) \
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_Generic((x), \
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__le64 : le64_to_cpu((x)), \
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__le32 : le32_to_cpu((x)), \
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__le16 : le16_to_cpu((x)) \
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)
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#define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) \
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(fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? \
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fsl_edma_le_to_cpu(((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
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fsl_edma_le_to_cpu(((struct fsl_edma_hw_tcd *)_tcd)->_field))
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#define fsl_edma_set_tcd_to_le_c(_tcd, _val, _field) \
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_Generic(((_tcd)->_field), \
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__le64 : (_tcd)->_field = cpu_to_le64(_val), \
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__le32 : (_tcd)->_field = cpu_to_le32(_val), \
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__le16 : (_tcd)->_field = cpu_to_le16(_val) \
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)
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#define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field) \
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do { \
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if (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64) \
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fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd64 *)_tcd, _val, _field); \
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else \
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fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd *)_tcd, _val, _field); \
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} while (0)
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/* Need after struct defination */
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#include "fsl-edma-trace.h"
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/*
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* R/W functions for big- or little-endian registers:
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* The eDMA controller's endian is independent of the CPU core's endian.
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* For the big-endian IP module, the offset for 8-bit or 16-bit registers
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* should also be swapped opposite to that in little-endian IP.
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*/
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static inline u64 edma_readq(struct fsl_edma_engine *edma, void __iomem *addr)
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{
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u64 l, h;
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if (edma->big_endian) {
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l = ioread32be(addr);
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h = ioread32be(addr + 4);
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} else {
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l = ioread32(addr);
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h = ioread32(addr + 4);
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}
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trace_edma_readl(edma, addr, l);
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trace_edma_readl(edma, addr + 4, h);
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return (h << 32) | l;
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}
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static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr)
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{
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u32 val;
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if (edma->big_endian)
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val = ioread32be(addr);
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else
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val = ioread32(addr);
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trace_edma_readl(edma, addr, val);
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return val;
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}
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static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
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{
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u16 val;
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if (edma->big_endian)
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val = ioread16be(addr);
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else
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val = ioread16(addr);
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trace_edma_readw(edma, addr, val);
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return val;
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}
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static inline void edma_writeb(struct fsl_edma_engine *edma,
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u8 val, void __iomem *addr)
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{
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/* swap the reg offset for these in big-endian mode */
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if (edma->big_endian)
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iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3));
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else
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iowrite8(val, addr);
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trace_edma_writeb(edma, addr, val);
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}
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static inline void edma_writew(struct fsl_edma_engine *edma,
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u16 val, void __iomem *addr)
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{
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/* swap the reg offset for these in big-endian mode */
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if (edma->big_endian)
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iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2));
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else
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iowrite16(val, addr);
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trace_edma_writew(edma, addr, val);
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}
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static inline void edma_writel(struct fsl_edma_engine *edma,
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u32 val, void __iomem *addr)
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{
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if (edma->big_endian)
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iowrite32be(val, addr);
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else
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iowrite32(val, addr);
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|
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trace_edma_writel(edma, addr, val);
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}
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static inline void edma_writeq(struct fsl_edma_engine *edma,
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u64 val, void __iomem *addr)
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{
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if (edma->big_endian) {
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iowrite32be(val & 0xFFFFFFFF, addr);
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iowrite32be(val >> 32, addr + 4);
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} else {
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iowrite32(val & 0xFFFFFFFF, addr);
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iowrite32(val >> 32, addr + 4);
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}
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|
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trace_edma_writel(edma, addr, val & 0xFFFFFFFF);
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trace_edma_writel(edma, addr + 4, val >> 32);
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}
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|
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static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan)
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|
{
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return container_of(chan, struct fsl_edma_chan, vchan.chan);
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|
}
|
|
|
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static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
|
|
{
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|
return container_of(vd, struct fsl_edma_desc, vdesc);
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|
}
|
|
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static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan)
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|
{
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|
fsl_chan->status = DMA_ERROR;
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|
}
|
|
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void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan);
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|
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
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|
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
|
|
unsigned int slot, bool enable);
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|
void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
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|
int fsl_edma_terminate_all(struct dma_chan *chan);
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|
int fsl_edma_pause(struct dma_chan *chan);
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|
int fsl_edma_resume(struct dma_chan *chan);
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|
int fsl_edma_slave_config(struct dma_chan *chan,
|
|
struct dma_slave_config *cfg);
|
|
enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
|
|
dma_cookie_t cookie, struct dma_tx_state *txstate);
|
|
struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
|
|
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
|
|
size_t period_len, enum dma_transfer_direction direction,
|
|
unsigned long flags);
|
|
struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
|
|
struct dma_chan *chan, struct scatterlist *sgl,
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
|
unsigned long flags, void *context);
|
|
struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(
|
|
struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src,
|
|
size_t len, unsigned long flags);
|
|
void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan);
|
|
void fsl_edma_issue_pending(struct dma_chan *chan);
|
|
int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
|
|
void fsl_edma_free_chan_resources(struct dma_chan *chan);
|
|
void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
|
|
void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
|
|
|
|
#endif /* _FSL_EDMA_COMMON_H_ */
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