Anson Huang 9ee417c074 regulators: anatop: add set_voltage_time_sel interface ... some of anatop's regulators(cpu, vddpu and vddsoc) have register settings about LDO's step time, which will impact the LDO ramp up speed, need to use set_voltage_time_sel interface to add necessary delay everytime LDOs' voltage is increased. offset 0x170: bit [24-25]: cpu bit [26-27]: vddpu bit [28-29]: vddsoc field definition: 0'b00: 64 cycles of 24M clock; 0'b01: 128 cycles of 24M clock; 0'b02: 256 cycles of 24M clock; 0'b03: 512 cycles of 24M clock; Signed-off-by: Anson Huang <b20788@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>		2013-01-31 14:40:49 +08:00
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bindings	regulators: anatop: add set_voltage_time_sel interface	2013-01-31 14:40:49 +08:00
00-INDEX	Documentation: add devicetree docs index file	2011-03-16 10:47:03 -07:00
booting-without-of.txt	dt/documentation: Fix value format description	2012-05-19 15:03:28 -06:00
usage-model.txt	Documentation: correct of_platform_populate() argument list	2012-11-21 15:53:23 +00:00