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Add support for configuring rates of, enabling, and disabling Alpha PLLs. This is sufficient for the types of PLLs found in the global and multimedia clock controllers. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
58 lines
1.4 KiB
C
58 lines
1.4 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_CLK_ALPHA_PLL_H__
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#define __QCOM_CLK_ALPHA_PLL_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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struct pll_vco {
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unsigned long min_freq;
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unsigned long max_freq;
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u32 val;
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};
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/**
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* struct clk_alpha_pll - phase locked loop (PLL)
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* @offset: base address of registers
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* @vco_table: array of VCO settings
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* @clkr: regmap clock handle
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*/
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struct clk_alpha_pll {
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u32 offset;
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const struct pll_vco *vco_table;
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size_t num_vco;
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struct clk_regmap clkr;
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};
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/**
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* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
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* @offset: base address of registers
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* @width: width of post-divider
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* @clkr: regmap clock handle
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*/
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struct clk_alpha_pll_postdiv {
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u32 offset;
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u8 width;
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_alpha_pll_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_ops;
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#endif
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