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In VLAN_AWARE mode CPSW can insert VLAN header encapsulation word on Host
port 0 egress (RX) before the packet data if RX_VLAN_ENCAP bit is set in
CPSW_CONTROL register. VLAN header encapsulation word has following format:
HDR_PKT_Priority bits 29-31 - Header Packet VLAN prio (Highest prio: 7)
HDR_PKT_CFI bits 28 - Header Packet VLAN CFI bit.
HDR_PKT_Vid bits 27-16 - Header Packet VLAN ID
PKT_Type bits 8-9 - Packet Type. Indicates whether the packet is
VLAN-tagged, priority-tagged, or non-tagged.
00: VLAN-tagged packet
01: Reserved
10: Priority-tagged packet
11: Non-tagged packet
This feature can be used to implement TX VLAN offload in case of
VLAN-tagged packets and to insert VLAN tag in case Non-tagged packet was
received on port with PVID set. As per documentation, CPSW never modifies
packet data on Host egress (RX) and as result, without this feature
enabled, Host port will not be able to receive properly packets which
entered switch non-tagged through external Port with PVID set (when
non-tagged packet forwarded from external Port with PVID set to another
external Port - packet will be VLAN tagged properly).
Implementation details:
- on RX driver will check CPDMA status bit RX_VLAN_ENCAP BIT(19) in CPPI
descriptor to identify when VLAN header encapsulation word is present.
- PKT_Type = 0x01 or 0x02 then ignore VLAN header encapsulation word and
pass packet as is;
- if HDR_PKT_Vid = 0 then ignore VLAN header encapsulation word and pass
packet as is;
- In dual mac mode traffic is separated between ports using default port
vlans, which are not be visible to Host and so should not be reported.
Hence, check for default port vlans in dual mac mode and ignore VLAN header
encapsulation word;
- otherwise fill SKB with VLAN info using __vlan_hwaccel_put_tag();
- PKT_Type = 0x00 (VLAN-tagged) then strip out VLAN header from SKB.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
125 lines
4.0 KiB
C
125 lines
4.0 KiB
C
/*
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* Texas Instruments CPDMA Driver
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*
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* Copyright (C) 2010 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DAVINCI_CPDMA_H__
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#define __DAVINCI_CPDMA_H__
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#define CPDMA_MAX_CHANNELS BITS_PER_LONG
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#define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7)
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#define CPDMA_RX_VLAN_ENCAP BIT(19)
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#define CPDMA_EOI_RX_THRESH 0x0
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#define CPDMA_EOI_RX 0x1
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#define CPDMA_EOI_TX 0x2
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#define CPDMA_EOI_MISC 0x3
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struct cpdma_params {
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struct device *dev;
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void __iomem *dmaregs;
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void __iomem *txhdp, *rxhdp, *txcp, *rxcp;
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void __iomem *rxthresh, *rxfree;
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int num_chan;
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bool has_soft_reset;
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int min_packet_size;
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u32 desc_mem_phys;
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u32 desc_hw_addr;
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int desc_mem_size;
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int desc_align;
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u32 bus_freq_mhz;
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u32 descs_pool_size;
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/*
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* Some instances of embedded cpdma controllers have extra control and
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* status registers. The following flag enables access to these
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* "extended" registers.
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*/
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bool has_ext_regs;
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};
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struct cpdma_chan_stats {
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u32 head_enqueue;
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u32 tail_enqueue;
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u32 pad_enqueue;
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u32 misqueued;
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u32 desc_alloc_fail;
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u32 pad_alloc_fail;
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u32 runt_receive_buff;
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u32 runt_transmit_buff;
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u32 empty_dequeue;
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u32 busy_dequeue;
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u32 good_dequeue;
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u32 requeue;
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u32 teardown_dequeue;
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};
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struct cpdma_ctlr;
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struct cpdma_chan;
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typedef void (*cpdma_handler_fn)(void *token, int len, int status);
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struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
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int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
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struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
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cpdma_handler_fn handler, int rx_type);
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int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan);
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int cpdma_chan_destroy(struct cpdma_chan *chan);
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int cpdma_chan_start(struct cpdma_chan *chan);
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int cpdma_chan_stop(struct cpdma_chan *chan);
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int cpdma_chan_get_stats(struct cpdma_chan *chan,
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struct cpdma_chan_stats *stats);
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int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
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int len, int directed);
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int cpdma_chan_process(struct cpdma_chan *chan, int quota);
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int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
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void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
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int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
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u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr);
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u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr);
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bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
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int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight);
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int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate);
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u32 cpdma_chan_get_rate(struct cpdma_chan *ch);
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u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr);
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enum cpdma_control {
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CPDMA_TX_RLIM, /* read-write */
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CPDMA_CMD_IDLE, /* write-only */
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CPDMA_COPY_ERROR_FRAMES, /* read-write */
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CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
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CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
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CPDMA_TX_PRIO_FIXED, /* read-write */
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CPDMA_STAT_IDLE, /* read-only */
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CPDMA_STAT_TX_ERR_CHAN, /* read-only */
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CPDMA_STAT_TX_ERR_CODE, /* read-only */
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CPDMA_STAT_RX_ERR_CHAN, /* read-only */
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CPDMA_STAT_RX_ERR_CODE, /* read-only */
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CPDMA_RX_BUFFER_OFFSET, /* read-write */
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};
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int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
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int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
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int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr);
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void cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc);
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int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr);
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int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr);
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#endif
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