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9964f396f1
Move enablement of mio addressing control from detect_machine_facilities
to pci_base_init. detect_machine_facilities runs so early that the
static branches have not been toggled yet, thus mio addressing control
was always off. In pci_base_init we have to use the SMP aware
ctl_set_bit though.
Fixes: 833b441ec0 ("s390: enable processes for mio instructions")
Signed-off-by: Sebastian Ott <sebott@linux.ibm.com>
Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
147 lines
3.7 KiB
C
147 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_S390_PCI_INSN_H
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#define _ASM_S390_PCI_INSN_H
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#include <linux/jump_label.h>
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/* Load/Store status codes */
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#define ZPCI_PCI_ST_FUNC_NOT_ENABLED 4
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#define ZPCI_PCI_ST_FUNC_IN_ERR 8
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#define ZPCI_PCI_ST_BLOCKED 12
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#define ZPCI_PCI_ST_INSUF_RES 16
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#define ZPCI_PCI_ST_INVAL_AS 20
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#define ZPCI_PCI_ST_FUNC_ALREADY_ENABLED 24
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#define ZPCI_PCI_ST_DMA_AS_NOT_ENABLED 28
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#define ZPCI_PCI_ST_2ND_OP_IN_INV_AS 36
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#define ZPCI_PCI_ST_FUNC_NOT_AVAIL 40
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#define ZPCI_PCI_ST_ALREADY_IN_RQ_STATE 44
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/* Load/Store return codes */
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#define ZPCI_PCI_LS_OK 0
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#define ZPCI_PCI_LS_ERR 1
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#define ZPCI_PCI_LS_BUSY 2
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#define ZPCI_PCI_LS_INVAL_HANDLE 3
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/* Load/Store address space identifiers */
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#define ZPCI_PCIAS_MEMIO_0 0
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#define ZPCI_PCIAS_MEMIO_1 1
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#define ZPCI_PCIAS_MEMIO_2 2
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#define ZPCI_PCIAS_MEMIO_3 3
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#define ZPCI_PCIAS_MEMIO_4 4
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#define ZPCI_PCIAS_MEMIO_5 5
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#define ZPCI_PCIAS_CFGSPC 15
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/* Modify PCI Function Controls */
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#define ZPCI_MOD_FC_REG_INT 2
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#define ZPCI_MOD_FC_DEREG_INT 3
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#define ZPCI_MOD_FC_REG_IOAT 4
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#define ZPCI_MOD_FC_DEREG_IOAT 5
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#define ZPCI_MOD_FC_REREG_IOAT 6
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#define ZPCI_MOD_FC_RESET_ERROR 7
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#define ZPCI_MOD_FC_RESET_BLOCK 9
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#define ZPCI_MOD_FC_SET_MEASURE 10
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#define ZPCI_MOD_FC_REG_INT_D 16
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#define ZPCI_MOD_FC_DEREG_INT_D 17
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/* FIB function controls */
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#define ZPCI_FIB_FC_ENABLED 0x80
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#define ZPCI_FIB_FC_ERROR 0x40
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#define ZPCI_FIB_FC_LS_BLOCKED 0x20
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#define ZPCI_FIB_FC_DMAAS_REG 0x10
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/* FIB function controls */
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#define ZPCI_FIB_FC_ENABLED 0x80
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#define ZPCI_FIB_FC_ERROR 0x40
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#define ZPCI_FIB_FC_LS_BLOCKED 0x20
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#define ZPCI_FIB_FC_DMAAS_REG 0x10
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struct zpci_fib_fmt0 {
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u32 : 1;
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u32 isc : 3; /* Interrupt subclass */
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u32 noi : 12; /* Number of interrupts */
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u32 : 2;
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u32 aibvo : 6; /* Adapter interrupt bit vector offset */
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u32 sum : 1; /* Adapter int summary bit enabled */
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u32 : 1;
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u32 aisbo : 6; /* Adapter int summary bit offset */
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u32 : 32;
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u64 aibv; /* Adapter int bit vector address */
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u64 aisb; /* Adapter int summary bit address */
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};
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struct zpci_fib_fmt1 {
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u32 : 4;
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u32 noi : 12;
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u32 : 16;
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u32 dibvo : 16;
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u32 : 16;
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u64 : 64;
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u64 : 64;
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};
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/* Function Information Block */
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struct zpci_fib {
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u32 fmt : 8; /* format */
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u32 : 24;
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u32 : 32;
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u8 fc; /* function controls */
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u64 : 56;
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u64 pba; /* PCI base address */
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u64 pal; /* PCI address limit */
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u64 iota; /* I/O Translation Anchor */
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union {
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struct zpci_fib_fmt0 fmt0;
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struct zpci_fib_fmt1 fmt1;
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};
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u64 fmb_addr; /* Function measurement block address and key */
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u32 : 32;
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u32 gd;
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} __packed __aligned(8);
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/* directed interruption information block */
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struct zpci_diib {
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u32 : 1;
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u32 isc : 3;
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u32 : 28;
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u16 : 16;
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u16 nr_cpus;
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u64 disb_addr;
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u64 : 64;
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u64 : 64;
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} __packed __aligned(8);
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/* cpu directed interruption information block */
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struct zpci_cdiib {
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u64 : 64;
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u64 dibv_addr;
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u64 : 64;
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u64 : 64;
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u64 : 64;
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} __packed __aligned(8);
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union zpci_sic_iib {
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struct zpci_diib diib;
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struct zpci_cdiib cdiib;
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};
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DECLARE_STATIC_KEY_FALSE(have_mio);
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u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status);
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int zpci_refresh_trans(u64 fn, u64 addr, u64 range);
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int __zpci_load(u64 *data, u64 req, u64 offset);
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int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len);
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int __zpci_store(u64 data, u64 req, u64 offset);
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int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len);
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int __zpci_store_block(const u64 *data, u64 req, u64 offset);
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void zpci_barrier(void);
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int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib);
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static inline int zpci_set_irq_ctrl(u16 ctl, u8 isc)
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{
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union zpci_sic_iib iib = {{0}};
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return __zpci_set_irq_ctrl(ctl, isc, &iib);
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}
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#endif
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