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287980e49f
Most users of IS_ERR_VALUE() in the kernel are wrong, as they pass an 'int' into a function that takes an 'unsigned long' argument. This happens to work because the type is sign-extended on 64-bit architectures before it gets converted into an unsigned type. However, anything that passes an 'unsigned short' or 'unsigned int' argument into IS_ERR_VALUE() is guaranteed to be broken, as are 8-bit integers and types that are wider than 'unsigned long'. Andrzej Hajda has already fixed a lot of the worst abusers that were causing actual bugs, but it would be nice to prevent any users that are not passing 'unsigned long' arguments. This patch changes all users of IS_ERR_VALUE() that I could find on 32-bit ARM randconfig builds and x86 allmodconfig. For the moment, this doesn't change the definition of IS_ERR_VALUE() because there are probably still architecture specific users elsewhere. Almost all the warnings I got are for files that are better off using 'if (err)' or 'if (err < 0)'. The only legitimate user I could find that we get a warning for is the (32-bit only) freescale fman driver, so I did not remove the IS_ERR_VALUE() there but changed the type to 'unsigned long'. For 9pfs, I just worked around one user whose calling conventions are so obscure that I did not dare change the behavior. I was using this definition for testing: #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \ unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO)) which ends up making all 16-bit or wider types work correctly with the most plausible interpretation of what IS_ERR_VALUE() was supposed to return according to its users, but also causes a compile-time warning for any users that do not pass an 'unsigned long' argument. I suggested this approach earlier this year, but back then we ended up deciding to just fix the users that are obviously broken. After the initial warning that caused me to get involved in the discussion (fs/gfs2/dir.c) showed up again in the mainline kernel, Linus asked me to send the whole thing again. [ Updated the 9p parts as per Al Viro - Linus ] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Andrew Morton <akpm@linux-foundation.org> Link: https://lkml.org/lkml/2016/1/7/363 Link: https://lkml.org/lkml/2016/5/27/486 Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
289 lines
7.3 KiB
C
289 lines
7.3 KiB
C
/*
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* SPEAr platform shared irq layer source file
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*
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* Copyright (C) 2009-2012 ST Microelectronics
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* Viresh Kumar <vireshk@kernel.org>
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*
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* Copyright (C) 2012 ST Microelectronics
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* Shiraz Hashim <shiraz.linux.kernel@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/spinlock.h>
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/*
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* struct spear_shirq: shared irq structure
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*
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* base: Base register address
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* status_reg: Status register offset for chained interrupt handler
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* mask_reg: Mask register offset for irq chip
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* mask: Mask to apply to the status register
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* virq_base: Base virtual interrupt number
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* nr_irqs: Number of interrupts handled by this block
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* offset: Bit offset of the first interrupt
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* irq_chip: Interrupt controller chip used for this instance,
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* if NULL group is disabled, but accounted
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*/
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struct spear_shirq {
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void __iomem *base;
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u32 status_reg;
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u32 mask_reg;
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u32 mask;
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u32 virq_base;
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u32 nr_irqs;
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u32 offset;
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struct irq_chip *irq_chip;
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};
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/* spear300 shared irq registers offsets and masks */
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#define SPEAR300_INT_ENB_MASK_REG 0x54
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#define SPEAR300_INT_STS_MASK_REG 0x58
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static DEFINE_RAW_SPINLOCK(shirq_lock);
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static void shirq_irq_mask(struct irq_data *d)
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{
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struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
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u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
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u32 __iomem *reg = shirq->base + shirq->mask_reg;
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raw_spin_lock(&shirq_lock);
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val = readl(reg) & ~(0x1 << shift);
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writel(val, reg);
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raw_spin_unlock(&shirq_lock);
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}
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static void shirq_irq_unmask(struct irq_data *d)
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{
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struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
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u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
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u32 __iomem *reg = shirq->base + shirq->mask_reg;
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raw_spin_lock(&shirq_lock);
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val = readl(reg) | (0x1 << shift);
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writel(val, reg);
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raw_spin_unlock(&shirq_lock);
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}
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static struct irq_chip shirq_chip = {
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.name = "spear-shirq",
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.irq_mask = shirq_irq_mask,
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.irq_unmask = shirq_irq_unmask,
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};
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static struct spear_shirq spear300_shirq_ras1 = {
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.offset = 0,
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.nr_irqs = 9,
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.mask = ((0x1 << 9) - 1) << 0,
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.irq_chip = &shirq_chip,
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.status_reg = SPEAR300_INT_STS_MASK_REG,
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.mask_reg = SPEAR300_INT_ENB_MASK_REG,
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};
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static struct spear_shirq *spear300_shirq_blocks[] = {
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&spear300_shirq_ras1,
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};
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/* spear310 shared irq registers offsets and masks */
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#define SPEAR310_INT_STS_MASK_REG 0x04
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static struct spear_shirq spear310_shirq_ras1 = {
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.offset = 0,
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.nr_irqs = 8,
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.mask = ((0x1 << 8) - 1) << 0,
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.irq_chip = &dummy_irq_chip,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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};
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static struct spear_shirq spear310_shirq_ras2 = {
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.offset = 8,
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.nr_irqs = 5,
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.mask = ((0x1 << 5) - 1) << 8,
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.irq_chip = &dummy_irq_chip,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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};
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static struct spear_shirq spear310_shirq_ras3 = {
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.offset = 13,
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.nr_irqs = 1,
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.mask = ((0x1 << 1) - 1) << 13,
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.irq_chip = &dummy_irq_chip,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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};
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static struct spear_shirq spear310_shirq_intrcomm_ras = {
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.offset = 14,
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.nr_irqs = 3,
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.mask = ((0x1 << 3) - 1) << 14,
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.irq_chip = &dummy_irq_chip,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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};
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static struct spear_shirq *spear310_shirq_blocks[] = {
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&spear310_shirq_ras1,
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&spear310_shirq_ras2,
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&spear310_shirq_ras3,
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&spear310_shirq_intrcomm_ras,
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};
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/* spear320 shared irq registers offsets and masks */
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#define SPEAR320_INT_STS_MASK_REG 0x04
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#define SPEAR320_INT_CLR_MASK_REG 0x04
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#define SPEAR320_INT_ENB_MASK_REG 0x08
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static struct spear_shirq spear320_shirq_ras3 = {
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.offset = 0,
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.nr_irqs = 7,
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.mask = ((0x1 << 7) - 1) << 0,
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};
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static struct spear_shirq spear320_shirq_ras1 = {
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.offset = 7,
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.nr_irqs = 3,
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.mask = ((0x1 << 3) - 1) << 7,
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.irq_chip = &dummy_irq_chip,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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};
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static struct spear_shirq spear320_shirq_ras2 = {
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.offset = 10,
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.nr_irqs = 1,
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.mask = ((0x1 << 1) - 1) << 10,
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.irq_chip = &dummy_irq_chip,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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};
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static struct spear_shirq spear320_shirq_intrcomm_ras = {
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.offset = 11,
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.nr_irqs = 11,
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.mask = ((0x1 << 11) - 1) << 11,
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.irq_chip = &dummy_irq_chip,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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};
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static struct spear_shirq *spear320_shirq_blocks[] = {
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&spear320_shirq_ras3,
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&spear320_shirq_ras1,
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&spear320_shirq_ras2,
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&spear320_shirq_intrcomm_ras,
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};
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static void shirq_handler(struct irq_desc *desc)
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{
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struct spear_shirq *shirq = irq_desc_get_handler_data(desc);
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u32 pend;
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pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
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pend >>= shirq->offset;
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while (pend) {
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int irq = __ffs(pend);
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pend &= ~(0x1 << irq);
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generic_handle_irq(shirq->virq_base + irq);
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}
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}
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static void __init spear_shirq_register(struct spear_shirq *shirq,
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int parent_irq)
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{
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int i;
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if (!shirq->irq_chip)
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return;
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irq_set_chained_handler_and_data(parent_irq, shirq_handler, shirq);
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for (i = 0; i < shirq->nr_irqs; i++) {
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irq_set_chip_and_handler(shirq->virq_base + i,
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shirq->irq_chip, handle_simple_irq);
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irq_set_chip_data(shirq->virq_base + i, shirq);
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}
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}
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static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
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struct device_node *np)
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{
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int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
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struct irq_domain *shirq_domain;
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void __iomem *base;
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("%s: failed to map shirq registers\n", __func__);
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return -ENXIO;
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}
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for (i = 0; i < block_nr; i++)
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nr_irqs += shirq_blocks[i]->nr_irqs;
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virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
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if (virq_base < 0) {
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pr_err("%s: irq desc alloc failed\n", __func__);
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goto err_unmap;
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}
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shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (WARN_ON(!shirq_domain)) {
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pr_warn("%s: irq domain init failed\n", __func__);
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goto err_free_desc;
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}
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for (i = 0; i < block_nr; i++) {
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shirq_blocks[i]->base = base;
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shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
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hwirq);
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parent_irq = irq_of_parse_and_map(np, i);
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spear_shirq_register(shirq_blocks[i], parent_irq);
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hwirq += shirq_blocks[i]->nr_irqs;
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}
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return 0;
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err_free_desc:
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irq_free_descs(virq_base, nr_irqs);
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err_unmap:
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iounmap(base);
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return -ENXIO;
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}
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static int __init spear300_shirq_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return shirq_init(spear300_shirq_blocks,
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ARRAY_SIZE(spear300_shirq_blocks), np);
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}
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IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
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static int __init spear310_shirq_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return shirq_init(spear310_shirq_blocks,
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ARRAY_SIZE(spear310_shirq_blocks), np);
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}
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IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
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static int __init spear320_shirq_of_init(struct device_node *np,
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struct device_node *parent)
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{
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return shirq_init(spear320_shirq_blocks,
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ARRAY_SIZE(spear320_shirq_blocks), np);
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}
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IRQCHIP_DECLARE(spear320_shirq, "st,spear320-shirq", spear320_shirq_of_init);
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