Peter De Schrijver 0b6525acd1 clk: tegra: Add PLL post divider table ... Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>		2013-04-04 16:10:45 -06:00
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clk-audio-sync.c
clk-divider.c
clk-periph-gate.c	clk: tegra: Fix periph_clk_to_bit macro	2013-04-04 16:08:27 -06:00
clk-periph.c	clk: tegra: Export peripheral reset functions	2013-04-04 16:08:31 -06:00
clk-pll-out.c
clk-pll.c	clk: tegra: Add PLL post divider table	2013-04-04 16:10:45 -06:00
clk-super.c	clk: tegra: Implement locking for super clock	2013-02-12 10:29:12 -07:00
clk-tegra20.c	clk: tegra: Add PLL post divider table	2013-04-04 16:10:45 -06:00
clk-tegra30.c	clk: tegra: Add PLL post divider table	2013-04-04 16:10:45 -06:00
clk.c	clk: tegra: provide dummy cpu car ops	2013-04-04 16:10:12 -06:00
clk.h	clk: tegra: Add PLL post divider table	2013-04-04 16:10:45 -06:00
Makefile	clk: tegra: add clock support for Tegra30	2013-01-28 11:19:07 -07:00