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76b17e6e49
We have found that we can sometimes see read failures on boards with high-capacitance SPI lines. It seems that the controller samples the Rx data line too early, and its register interface has an "Rx Sample Delay" setting to fine-tune against this issue. This patch adds a new optional device tree entry that can configure this delay in terms of nanoseconds. The kernel will calculate the best-fitting amount of parent clock ticks to program the controller with based on that. Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
46 lines
1.6 KiB
Plaintext
46 lines
1.6 KiB
Plaintext
* Rockchip SPI Controller
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The Rockchip SPI controller is used to interface with various devices such as flash
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and display controllers using the SPI communication interface.
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Required Properties:
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- compatible: should be one of the following.
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"rockchip,rk3066-spi" for rk3066.
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"rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188.
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"rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: The interrupt number to the cpu. The interrupt specifier format
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depends on the interrupt controller.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for
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the peripheral clock.
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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Optional Properties:
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- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
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Documentation/devicetree/bindings/dma/dma.txt
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- dma-names: DMA request names should include "tx" and "rx" if present.
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- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
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Rx data (may need to be fine tuned for high capacitance lines).
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No delay (0) by default.
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Example:
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spi0: spi@ff110000 {
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compatible = "rockchip,rk3066-spi";
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reg = <0xff110000 0x1000>;
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dmas = <&pdma1 11>, <&pdma1 12>;
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dma-names = "tx", "rx";
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rx-sample-delay-ns = <10>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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clock-names = "spiclk", "apb_pclk";
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};
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