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53c2df2f4e
Many RTC routines were not protected against each other, so there are
potential races, for example, ntp-update against /dev/rtc. This patch
fixes them using rtc_lock.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
233 lines
6.7 KiB
C
233 lines
6.7 KiB
C
/*
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* Copyright (C) 2000, 2001 Broadcom Corporation
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/bcd.h>
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#include <linux/types.h>
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#include <linux/time.h>
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#include <asm/time.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/sb1250_regs.h>
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#include <asm/sibyte/sb1250_smbus.h>
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/* M41T81 definitions */
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/*
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* Register bits
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*/
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#define M41T81REG_SC_ST 0x80 /* stop bit */
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#define M41T81REG_HR_CB 0x40 /* century bit */
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#define M41T81REG_HR_CEB 0x80 /* century enable bit */
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#define M41T81REG_CTL_S 0x20 /* sign bit */
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#define M41T81REG_CTL_FT 0x40 /* frequency test bit */
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#define M41T81REG_CTL_OUT 0x80 /* output level */
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#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */
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#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */
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#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */
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#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */
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#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */
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#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */
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#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */
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#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */
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#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */
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#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */
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#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */
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#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */
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#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */
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#define M41T81REG_AHR_HT 0x40 /* halt update bit */
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#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */
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#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */
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#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */
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#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */
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#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */
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#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */
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#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */
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#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */
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/*
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* Register numbers
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*/
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#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */
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#define M41T81REG_SC 0x01 /* seconds */
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#define M41T81REG_MN 0x02 /* minute */
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#define M41T81REG_HR 0x03 /* hour/century */
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#define M41T81REG_DY 0x04 /* day of week */
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#define M41T81REG_DT 0x05 /* date of month */
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#define M41T81REG_MO 0x06 /* month */
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#define M41T81REG_YR 0x07 /* year */
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#define M41T81REG_CTL 0x08 /* control */
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#define M41T81REG_WD 0x09 /* watchdog */
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#define M41T81REG_AMO 0x0A /* alarm: month */
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#define M41T81REG_ADT 0x0B /* alarm: date */
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#define M41T81REG_AHR 0x0C /* alarm: hour */
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#define M41T81REG_AMN 0x0D /* alarm: minute */
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#define M41T81REG_ASC 0x0E /* alarm: second */
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#define M41T81REG_FLG 0x0F /* flags */
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#define M41T81REG_SQW 0x13 /* square wave register */
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#define M41T81_CCR_ADDRESS 0x68
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#define SMB_CSR(reg) IOADDR(A_SMB_REGISTER(1, reg))
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static int m41t81_read(uint8_t addr)
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{
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while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
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;
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__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
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__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE,
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SMB_CSR(R_SMB_START));
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while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
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;
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__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
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SMB_CSR(R_SMB_START));
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while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
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;
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if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
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/* Clear error bit by writing a 1 */
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__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
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return -1;
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}
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return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
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}
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static int m41t81_write(uint8_t addr, int b)
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{
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while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
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;
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__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
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__raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));
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__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
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SMB_CSR(R_SMB_START));
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while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
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;
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if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
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/* Clear error bit by writing a 1 */
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__raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
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return -1;
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}
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/* read the same byte again to make sure it is written */
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__raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
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SMB_CSR(R_SMB_START));
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while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
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;
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return 0;
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}
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int m41t81_set_time(unsigned long t)
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{
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struct rtc_time tm;
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unsigned long flags;
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to_tm(t, &tm);
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/*
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* Note the write order matters as it ensures the correctness.
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* When we write sec, 10th sec is clear. It is reasonable to
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* believe we should finish writing min within a second.
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*/
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spin_lock_irqsave(&rtc_lock, flags);
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tm.tm_sec = BIN2BCD(tm.tm_sec);
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m41t81_write(M41T81REG_SC, tm.tm_sec);
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tm.tm_min = BIN2BCD(tm.tm_min);
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m41t81_write(M41T81REG_MN, tm.tm_min);
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tm.tm_hour = BIN2BCD(tm.tm_hour);
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tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0);
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m41t81_write(M41T81REG_HR, tm.tm_hour);
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/* tm_wday starts from 0 to 6 */
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if (tm.tm_wday == 0) tm.tm_wday = 7;
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tm.tm_wday = BIN2BCD(tm.tm_wday);
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m41t81_write(M41T81REG_DY, tm.tm_wday);
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tm.tm_mday = BIN2BCD(tm.tm_mday);
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m41t81_write(M41T81REG_DT, tm.tm_mday);
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/* tm_mon starts from 0, *ick* */
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tm.tm_mon ++;
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tm.tm_mon = BIN2BCD(tm.tm_mon);
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m41t81_write(M41T81REG_MO, tm.tm_mon);
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/* we don't do century, everything is beyond 2000 */
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tm.tm_year %= 100;
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tm.tm_year = BIN2BCD(tm.tm_year);
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m41t81_write(M41T81REG_YR, tm.tm_year);
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spin_unlock_irqrestore(&rtc_lock, flags);
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return 0;
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}
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unsigned long m41t81_get_time(void)
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{
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unsigned int year, mon, day, hour, min, sec;
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unsigned long flags;
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/*
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* min is valid if two reads of sec are the same.
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*/
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for (;;) {
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spin_lock_irqsave(&rtc_lock, flags);
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sec = m41t81_read(M41T81REG_SC);
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min = m41t81_read(M41T81REG_MN);
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if (sec == m41t81_read(M41T81REG_SC)) break;
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spin_unlock_irqrestore(&rtc_lock, flags);
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}
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hour = m41t81_read(M41T81REG_HR) & 0x3f;
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day = m41t81_read(M41T81REG_DT);
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mon = m41t81_read(M41T81REG_MO);
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year = m41t81_read(M41T81REG_YR);
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spin_unlock_irqrestore(&rtc_lock, flags);
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sec = BCD2BIN(sec);
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min = BCD2BIN(min);
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hour = BCD2BIN(hour);
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day = BCD2BIN(day);
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mon = BCD2BIN(mon);
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year = BCD2BIN(year);
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year += 2000;
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return mktime(year, mon, day, hour, min, sec);
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}
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int m41t81_probe(void)
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{
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unsigned int tmp;
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/* enable chip if it is not enabled yet */
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tmp = m41t81_read(M41T81REG_SC);
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m41t81_write(M41T81REG_SC, tmp & 0x7f);
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return (m41t81_read(M41T81REG_SC) != -1);
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}
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