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0a441514bc
The correct MT8192 CFG register base is 0x20000 off. Changes the
registers accordingly.
Fixes: fd0b6c1ff8 ("remoteproc/mediatek: Add support for mt8192 SCP")
Signed-off-by: Tzung-Bi Shih <tzungbi@google.com>
Link: https://lore.kernel.org/r/20201210054109.587795-1-tzungbi@google.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __RPROC_MTK_COMMON_H
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#define __RPROC_MTK_COMMON_H
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/remoteproc.h>
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#include <linux/remoteproc/mtk_scp.h>
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#define MT8183_SW_RSTN 0x0
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#define MT8183_SW_RSTN_BIT BIT(0)
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#define MT8183_SCP_TO_HOST 0x1C
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#define MT8183_SCP_IPC_INT_BIT BIT(0)
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#define MT8183_SCP_WDT_INT_BIT BIT(8)
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#define MT8183_HOST_TO_SCP 0x28
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#define MT8183_HOST_IPC_INT_BIT BIT(0)
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#define MT8183_WDT_CFG 0x84
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#define MT8183_SCP_CLK_SW_SEL 0x4000
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#define MT8183_SCP_CLK_DIV_SEL 0x4024
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#define MT8183_SCP_SRAM_PDN 0x402C
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#define MT8183_SCP_L1_SRAM_PD 0x4080
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#define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094
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#define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000)
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#define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0)
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#define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1)
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#define MT8183_SCP_CACHESIZE_8KB BIT(8)
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#define MT8183_SCP_CACHE_CON_WAYEN BIT(10)
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#define MT8192_L2TCM_SRAM_PD_0 0x10C0
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#define MT8192_L2TCM_SRAM_PD_1 0x10C4
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#define MT8192_L2TCM_SRAM_PD_2 0x10C8
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#define MT8192_L1TCM_SRAM_PDN 0x102C
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#define MT8192_CPU0_SRAM_PD 0x1080
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#define MT8192_SCP2APMCU_IPC_SET 0x4080
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#define MT8192_SCP2APMCU_IPC_CLR 0x4084
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#define MT8192_SCP_IPC_INT_BIT BIT(0)
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#define MT8192_SCP2SPM_IPC_CLR 0x4094
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#define MT8192_GIPC_IN_SET 0x4098
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#define MT8192_HOST_IPC_INT_BIT BIT(0)
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#define MT8192_CORE0_SW_RSTN_CLR 0x10000
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#define MT8192_CORE0_SW_RSTN_SET 0x10004
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#define MT8192_CORE0_WDT_CFG 0x10034
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#define SCP_FW_VER_LEN 32
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#define SCP_SHARE_BUFFER_SIZE 288
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struct scp_run {
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u32 signaled;
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s8 fw_ver[SCP_FW_VER_LEN];
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u32 dec_capability;
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u32 enc_capability;
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wait_queue_head_t wq;
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};
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struct scp_ipi_desc {
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/* For protecting handler. */
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struct mutex lock;
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scp_ipi_handler_t handler;
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void *priv;
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};
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struct mtk_scp;
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struct mtk_scp_of_data {
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int (*scp_before_load)(struct mtk_scp *scp);
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void (*scp_irq_handler)(struct mtk_scp *scp);
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void (*scp_reset_assert)(struct mtk_scp *scp);
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void (*scp_reset_deassert)(struct mtk_scp *scp);
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void (*scp_stop)(struct mtk_scp *scp);
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u32 host_to_scp_reg;
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u32 host_to_scp_int_bit;
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};
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struct mtk_scp {
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struct device *dev;
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struct rproc *rproc;
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struct clk *clk;
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void __iomem *reg_base;
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void __iomem *sram_base;
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size_t sram_size;
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const struct mtk_scp_of_data *data;
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struct mtk_share_obj __iomem *recv_buf;
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struct mtk_share_obj __iomem *send_buf;
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struct scp_run run;
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/* To prevent multiple ipi_send run concurrently. */
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struct mutex send_lock;
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struct scp_ipi_desc ipi_desc[SCP_IPI_MAX];
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bool ipi_id_ack[SCP_IPI_MAX];
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wait_queue_head_t ack_wq;
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void *cpu_addr;
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dma_addr_t dma_addr;
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size_t dram_size;
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struct rproc_subdev *rpmsg_subdev;
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};
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/**
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* struct mtk_share_obj - SRAM buffer shared with AP and SCP
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*
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* @id: IPI id
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* @len: share buffer length
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* @share_buf: share buffer data
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*/
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struct mtk_share_obj {
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u32 id;
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u32 len;
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u8 share_buf[SCP_SHARE_BUFFER_SIZE];
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};
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void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len);
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void scp_ipi_lock(struct mtk_scp *scp, u32 id);
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void scp_ipi_unlock(struct mtk_scp *scp, u32 id);
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#endif
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