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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
136 lines
5.0 KiB
C
136 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* MPC85xx/86xx PCI Express structure define
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*
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* Copyright 2007,2011 Freescale Semiconductor, Inc
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*/
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#ifdef __KERNEL__
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#ifndef __POWERPC_FSL_PCI_H
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#define __POWERPC_FSL_PCI_H
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struct platform_device;
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/* FSL PCI controller BRR1 register */
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#define PCI_FSL_BRR1 0xbf8
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#define PCI_FSL_BRR1_VER 0xffff
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#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
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#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
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#define PIWAR_EN 0x80000000 /* Enable */
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#define PIWAR_PF 0x20000000 /* prefetch */
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#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
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#define PIWAR_READ_SNOOP 0x00050000
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#define PIWAR_WRITE_SNOOP 0x00005000
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#define PIWAR_SZ_MASK 0x0000003f
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#define PEX_PMCR_PTOMR 0x1
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#define PEX_PMCR_EXL2S 0x2
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#define PME_DISR_EN_PTOD 0x00008000
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#define PME_DISR_EN_ENL23D 0x00002000
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#define PME_DISR_EN_EXL23D 0x00001000
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/* PCI/PCI Express outbound window reg */
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struct pci_outbound_window_regs {
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__be32 potar; /* 0x.0 - Outbound translation address register */
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__be32 potear; /* 0x.4 - Outbound translation extended address register */
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__be32 powbar; /* 0x.8 - Outbound window base address register */
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u8 res1[4];
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__be32 powar; /* 0x.10 - Outbound window attributes register */
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u8 res2[12];
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};
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/* PCI/PCI Express inbound window reg */
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struct pci_inbound_window_regs {
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__be32 pitar; /* 0x.0 - Inbound translation address register */
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u8 res1[4];
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__be32 piwbar; /* 0x.8 - Inbound window base address register */
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__be32 piwbear; /* 0x.c - Inbound window base extended address register */
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__be32 piwar; /* 0x.10 - Inbound window attributes register */
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u8 res2[12];
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};
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/* PCI/PCI Express IO block registers for 85xx/86xx */
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struct ccsr_pci {
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__be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
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__be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
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__be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
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__be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
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__be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
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__be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
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__be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
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u8 res2[4];
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__be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
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__be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
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__be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
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__be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
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u8 res3[3016];
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__be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
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__be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
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/* PCI/PCI Express outbound window 0-4
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* Window 0 is the default window and is the only window enabled upon reset.
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* The default outbound register set is used when a transaction misses
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* in all of the other outbound windows.
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*/
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struct pci_outbound_window_regs pow[5];
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u8 res14[96];
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struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
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u8 res6[96];
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/* PCI/PCI Express inbound window 3-0
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* inbound window 1 supports only a 32-bit base address and does not
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* define an inbound window base extended address register.
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*/
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struct pci_inbound_window_regs piw[4];
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__be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
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u8 res21[4];
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__be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
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u8 res22[4];
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__be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
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u8 res23[12];
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__be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
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u8 res24[4];
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__be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
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__be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
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__be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
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__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
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u8 res_e38[200];
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__be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
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u8 res_f04[16];
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__be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
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#define PEX_CSR0_LTSSM_MASK 0xFC
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#define PEX_CSR0_LTSSM_SHIFT 2
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#define PEX_CSR0_LTSSM_L0 0x11
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__be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
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u8 res_f1c[228];
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};
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extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
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extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
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extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
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extern int mpc83xx_add_bridge(struct device_node *dev);
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u64 fsl_pci_immrbar_base(struct pci_controller *hose);
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extern struct device_node *fsl_pci_primary;
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#ifdef CONFIG_PCI
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void fsl_pci_assign_primary(void);
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#else
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static inline void fsl_pci_assign_primary(void) {}
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#endif
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#ifdef CONFIG_FSL_PCI
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extern int fsl_pci_mcheck_exception(struct pt_regs *);
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#else
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static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
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#endif
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#endif /* __POWERPC_FSL_PCI_H */
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#endif /* __KERNEL__ */
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