mirror of
https://github.com/torvalds/linux.git
synced 2024-12-26 12:52:30 +00:00
0890a26479
ARCv2 is the next generation ISA from Synopsys and basis for the
HS3{4,6,8} families of processors which retain the traditional ARC mantra of
low power and configurability and are now more performant and feature rich.
HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and
SMP (upto 4 cores) among other features.
+ www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor
+ http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications
+ http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps
- Support for ARC SDP (Software Development platform): Main Board + CPU Cards
= AXS101: CPU Card with ARC700 in silicon @ 700 MHz
= AXS103: CPU Card with HS38x in FPGA
- Refactoring of ARCompact port to accomodate new ARCv2 ISA
- Miscll updates/cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVk0g8AAoJEGnX8d3iisJecqsQAI6gvBC4GSNYDrmgGJJK1uLQ
uf6ZXQRLBtyxwa6VMvaNFe91i5XV5WvEXDuNBQX4FdYbp7Fs+Jz5VK79xFtbVEdU
H6mgKcs9HBwQvrHBxl54XxxXfX7kD1kxrlV7cL4b7bXTEX0XyH5ROUj600/YP+B4
8t+XdYcfgFK0HpeFGXVP+Xmv/e+hBbzCpOjOd2ZFqEwymvSpZDc4KZ2yDvV2+Ybn
JNZ421urQOrxR27njvvPvtpeN7uuJKfRYq7IuIR8+Ad72S19EDdw+DZHp2XoUMXA
wgydWrrOaX2Dr2CmXHGA1C4nWEG7+Yo9I1WitjJct0tkOQyDR2OIDGmvKGBd1uoS
QsihtoKBRvns+2gpXBEOmOHmF6ggpHNN0ppIwCp+AK5kX3fmxBtyUekyYmVpg8oQ
xgFIuJgmiAvW7QB7xIO6SFFt18De2ifDRrKWJwVauvfW/PvUIwuUBEcbh0OHAn54
ebUUWu2ZdVNe0XCsZOAQGwYHZRWBk8Bn3bhFpNnOliRiF77e9GsKeGYeIswYFy7I
42Gp35ftEj1pLLFZ1vIsAo72N6ErmHwPOcJkaBYaTbPGPcTEO2aR6b8WOcCjsPxK
DUeUV3H2HV+6V4jw/96lnsaRqsaj4TsJxEAFRR3wT1DLoRudCIDubaXTdvvDie77
RgKn4ZdxgmXD97+deBqc
=KwNo
-----END PGP SIGNATURE-----
Merge tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC architecture updates from Vineet Gupta:
- support for HS38 cores based on ARCv2 ISA
ARCv2 is the next generation ISA from Synopsys and basis for the
HS3{4,6,8} families of processors which retain the traditional ARC mantra of
low power and configurability and are now more performant and feature rich.
HS38x is a 10 stage pipeline core which supports MMU (with huge pages) and
SMP (upto 4 cores) among other features.
+ www.synopsys.com/dw/ipdir.php?ds=arc-hs38-processor
+ http://news.synopsys.com/2014-10-14-New-DesignWare-ARC-HS38-Processor-Doubles-Performance-for-Embedded-Linux-Applications
+ http://www.embedded.com/electronics-news/4435975/Synopsys-ARC-HS38-core-gives-2X-boost-to-Linux-based-apps
- support for ARC SDP (Software Development platform): Main Board + CPU Cards
= AXS101: CPU Card with ARC700 in silicon @ 700 MHz
= AXS103: CPU Card with HS38x in FPGA
- refactoring of ARCompact port to accomodate new ARCv2 ISA
- misc updates/cleanups
* tag 'arc-4.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (72 commits)
ARC: Fix build failures for ARCompact in linux-next after ARCv2 support
ARCv2: Allow older gcc to cope with new regime of ARCv2/ARCompact support
ARCv2: [vdk] dts files and defconfig for HS38 VDK
ARCv2: [axs103] Support ARC SDP FPGA platform for HS38x cores
ARC: [axs101] Prepare for AXS103
ARCv2: [nsim*hs*] Support simulation platforms for HS38x cores
ARCv2: All bits in place, allow ARCv2 builds
ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)
ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock
ARC: Reduce bitops lines of code using macros
ARCv2: barriers
arch: conditionally define smp_{mb,rmb,wmb}
ARC: add smp barriers around atomics per Documentation/atomic_ops.txt
ARC: add compiler barrier to LLSC based cmpxchg
ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution
ARCv2: SMP: clocksource: Enable Global Real Time counter
ARCv2: SMP: ARConnect debug/robustness
ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al
ARC: make plat_smp_ops weak to allow over-rides
ARCv2: clocksource: Introduce 64bit local RTC counter
...
145 lines
3.4 KiB
C
145 lines
3.4 KiB
C
/*
|
|
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef _ASM_ARC_IO_H
|
|
#define _ASM_ARC_IO_H
|
|
|
|
#include <linux/types.h>
|
|
#include <asm/byteorder.h>
|
|
#include <asm/page.h>
|
|
|
|
extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);
|
|
extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
|
|
unsigned long flags);
|
|
extern void iounmap(const void __iomem *addr);
|
|
|
|
#define ioremap_nocache(phy, sz) ioremap(phy, sz)
|
|
#define ioremap_wc(phy, sz) ioremap(phy, sz)
|
|
#define ioremap_wt(phy, sz) ioremap(phy, sz)
|
|
|
|
/* Change struct page to physical address */
|
|
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
|
|
|
|
#define __raw_readb __raw_readb
|
|
static inline u8 __raw_readb(const volatile void __iomem *addr)
|
|
{
|
|
u8 b;
|
|
|
|
__asm__ __volatile__(
|
|
" ldb%U1 %0, %1 \n"
|
|
: "=r" (b)
|
|
: "m" (*(volatile u8 __force *)addr)
|
|
: "memory");
|
|
|
|
return b;
|
|
}
|
|
|
|
#define __raw_readw __raw_readw
|
|
static inline u16 __raw_readw(const volatile void __iomem *addr)
|
|
{
|
|
u16 s;
|
|
|
|
__asm__ __volatile__(
|
|
" ldw%U1 %0, %1 \n"
|
|
: "=r" (s)
|
|
: "m" (*(volatile u16 __force *)addr)
|
|
: "memory");
|
|
|
|
return s;
|
|
}
|
|
|
|
#define __raw_readl __raw_readl
|
|
static inline u32 __raw_readl(const volatile void __iomem *addr)
|
|
{
|
|
u32 w;
|
|
|
|
__asm__ __volatile__(
|
|
" ld%U1 %0, %1 \n"
|
|
: "=r" (w)
|
|
: "m" (*(volatile u32 __force *)addr)
|
|
: "memory");
|
|
|
|
return w;
|
|
}
|
|
|
|
#define __raw_writeb __raw_writeb
|
|
static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
|
|
{
|
|
__asm__ __volatile__(
|
|
" stb%U1 %0, %1 \n"
|
|
:
|
|
: "r" (b), "m" (*(volatile u8 __force *)addr)
|
|
: "memory");
|
|
}
|
|
|
|
#define __raw_writew __raw_writew
|
|
static inline void __raw_writew(u16 s, volatile void __iomem *addr)
|
|
{
|
|
__asm__ __volatile__(
|
|
" stw%U1 %0, %1 \n"
|
|
:
|
|
: "r" (s), "m" (*(volatile u16 __force *)addr)
|
|
: "memory");
|
|
|
|
}
|
|
|
|
#define __raw_writel __raw_writel
|
|
static inline void __raw_writel(u32 w, volatile void __iomem *addr)
|
|
{
|
|
__asm__ __volatile__(
|
|
" st%U1 %0, %1 \n"
|
|
:
|
|
: "r" (w), "m" (*(volatile u32 __force *)addr)
|
|
: "memory");
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_ISA_ARCV2
|
|
#include <asm/barrier.h>
|
|
#define __iormb() rmb()
|
|
#define __iowmb() wmb()
|
|
#else
|
|
#define __iormb() do { } while (0)
|
|
#define __iowmb() do { } while (0)
|
|
#endif
|
|
|
|
/*
|
|
* MMIO can also get buffered/optimized in micro-arch, so barriers needed
|
|
* Based on ARM model for the typical use case
|
|
*
|
|
* <ST [DMA buffer]>
|
|
* <writel MMIO "go" reg>
|
|
* or:
|
|
* <readl MMIO "status" reg>
|
|
* <LD [DMA buffer]>
|
|
*
|
|
* http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
|
|
*/
|
|
#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
|
|
#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
|
|
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
|
|
|
|
#define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
|
|
#define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
|
|
#define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
|
|
|
|
/*
|
|
* Relaxed API for drivers which can handle any ordering themselves
|
|
*/
|
|
#define readb_relaxed(c) __raw_readb(c)
|
|
#define readw_relaxed(c) __raw_readw(c)
|
|
#define readl_relaxed(c) __raw_readl(c)
|
|
|
|
#define writeb_relaxed(v,c) __raw_writeb(v,c)
|
|
#define writew_relaxed(v,c) __raw_writew(v,c)
|
|
#define writel_relaxed(v,c) __raw_writel(v,c)
|
|
|
|
#include <asm-generic/io.h>
|
|
|
|
#endif /* _ASM_ARC_IO_H */
|