mirror of
https://github.com/torvalds/linux.git
synced 2024-12-29 14:21:47 +00:00
9bbd4b9f38
- DT binding doc consolidation moving similar bindings to common locations. The majority of these are display related which were scattered in video/, fb/, drm/, gpu/, and panel/ directories. - Add new config option, CONFIG_OF_ALL_DTBS, to enable building all dtbs in the tree for most arches with dts files (except powerpc for now). - OF_IRQ=n fixes for user enabled CONFIG_OF. - of_node_put ref counting fixes from Julia Lawall. - Common DT binding for wakeup-source and deprecation of all similar bindings. - DT binding for PXA LCD controller. - Allow ignoring failed PCI resource translations in order to ignore 64-bit addresses on non-LPAE 32-bit kernels. - Support setting the NUMA node from DT instead of only from parent device. - Couple of earlycon DT parsing fixes for address and options. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWO+HwAAoJEPr7XbWNvGHDFOoP/RcK4z5dtVQL2XRFbJBqRBZU riMc4BZkwpcKGXjzZlMrLw+mg4vaoLKSIAGAsYkgdDOKbYphQQdVwDzN099Fzpzy EE6K7Q+AW618z34AWdDjcpJYzSFnjAjYdh6JabohmKdPlxobR1RsKT+nRpDOGfeO c1DmxAQ1Fiav+xAI4m0YUuyxQDUeFYC0mVcVPzRbWZj31Ia5BgIrvT+V7fM55CTb dOAYWDHrfOw+yYI98sqZoSAb5H+E3UuY1ymBMhiP16Ot2vCyIKRYwhDokF9VYO/0 MpIMhCgv1jmE5NCbBeYSSJUePySvvnuyYe6HIaJQjV8KGEZ5C7c1iLMgtvov2KVI bcSx6nPH/u5FuWIhWdMINPc50AQBAK/akYcgoCVjioVX+4WY2pqLvsXW2arEr//Z XY3FUpgS6eI42HBsj4SxrGnzaRc2jPOs6yiANkywmHnpWcyvszCxUEvf0Mh0cbkm diu31/owdpUO5imCe+ErtGVV3vY2VUMnbcm8J61pqL52OZNPLZUUEfktv1JCGW7y cVdnlgeGSFuCbY4jUErvxtQGJQLFwf7Gg1U/VfFXX2iuQGAACB1KwxY5sR6P5Ghz W6NvOTT36kaM9WGqn/bquOd6EmKcx9aZfgRLOkgV86Q/11gHKpuRjkrsth7rIJDI 97qkGiWl4t1Ll5T4StK8 =tGCy -----END PGP SIGNATURE----- Merge tag 'devicetree-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull DeviceTree updates from Rob Herring: "A fairly large (by DT standards) pull request this time with the majority being some overdue moving DT binding docs around to consolidate similar bindings. - DT binding doc consolidation moving similar bindings to common locations. The majority of these are display related which were scattered in video/, fb/, drm/, gpu/, and panel/ directories. - Add new config option, CONFIG_OF_ALL_DTBS, to enable building all dtbs in the tree for most arches with dts files (except powerpc for now). - OF_IRQ=n fixes for user enabled CONFIG_OF. - of_node_put ref counting fixes from Julia Lawall. - Common DT binding for wakeup-source and deprecation of all similar bindings. - DT binding for PXA LCD controller. - Allow ignoring failed PCI resource translations in order to ignore 64-bit addresses on non-LPAE 32-bit kernels. - Support setting the NUMA node from DT instead of only from parent device. - Couple of earlycon DT parsing fixes for address and options" * tag 'devicetree-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (45 commits) MAINTAINERS: update DT binding doc locations devicetree: add Sigma Designs vendor prefix of: simplify arch_find_n_match_cpu_physical_id() function Documentation: arm: Fixed typo in socfpga fpga mgr example Documentation: devicetree: fix reference to legacy wakeup properties Documentation: devicetree: standardize/consolidate on "wakeup-source" property drivers: of: removing assignment of 0 to static variable xtensa: enable building of all dtbs mips: enable building of all dtbs metag: enable building of all dtbs metag: use common make variables for dtb builds h8300: enable building of all dtbs arm64: enable building of all dtbs arm: enable building of all dtbs arc: enable building of all dtbs arc: use common make variables for dtb builds of: add config option to enable building of all dtbs of/fdt: fix error checking for earlycon address of/overlay: add missing of_node_put of/platform: add missing of_node_put ...
169 lines
5.2 KiB
Plaintext
169 lines
5.2 KiB
Plaintext
* ARM Generic Interrupt Controller
|
|
|
|
ARM SMP cores are often associated with a GIC, providing per processor
|
|
interrupts (PPI), shared processor interrupts (SPI) and software
|
|
generated interrupts (SGI).
|
|
|
|
Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
|
|
Secondary GICs are cascaded into the upward interrupt controller and do not
|
|
have PPIs or SGIs.
|
|
|
|
Main node required properties:
|
|
|
|
- compatible : should be one of:
|
|
"arm,arm1176jzf-devchip-gic"
|
|
"arm,arm11mp-gic"
|
|
"arm,cortex-a15-gic"
|
|
"arm,cortex-a7-gic"
|
|
"arm,cortex-a9-gic"
|
|
"arm,gic-400"
|
|
"arm,pl390"
|
|
"brcm,brahma-b15-gic"
|
|
"qcom,msm-8660-qgic"
|
|
"qcom,msm-qgic2"
|
|
- interrupt-controller : Identifies the node as an interrupt controller
|
|
- #interrupt-cells : Specifies the number of cells needed to encode an
|
|
interrupt source. The type shall be a <u32> and the value shall be 3.
|
|
|
|
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
|
|
interrupts.
|
|
|
|
The 2nd cell contains the interrupt number for the interrupt type.
|
|
SPI interrupts are in the range [0-987]. PPI interrupts are in the
|
|
range [0-15].
|
|
|
|
The 3rd cell is the flags, encoded as follows:
|
|
bits[3:0] trigger type and level flags.
|
|
1 = low-to-high edge triggered
|
|
2 = high-to-low edge triggered (invalid for SPIs)
|
|
4 = active high level-sensitive
|
|
8 = active low level-sensitive (invalid for SPIs).
|
|
bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
|
|
the 8 possible cpus attached to the GIC. A bit set to '1' indicated
|
|
the interrupt is wired to that CPU. Only valid for PPI interrupts.
|
|
Also note that the configurability of PPI interrupts is IMPLEMENTATION
|
|
DEFINED and as such not guaranteed to be present (most SoC available
|
|
in 2014 seem to ignore the setting of this flag and use the hardware
|
|
default value).
|
|
|
|
- reg : Specifies base physical address(s) and size of the GIC registers. The
|
|
first region is the GIC distributor register base and size. The 2nd region is
|
|
the GIC cpu interface register base and size.
|
|
|
|
Optional
|
|
- interrupts : Interrupt source of the parent interrupt controller on
|
|
secondary GICs, or VGIC maintenance interrupt on primary GIC (see
|
|
below).
|
|
|
|
- cpu-offset : per-cpu offset within the distributor and cpu interface
|
|
regions, used when the GIC doesn't have banked registers. The offset is
|
|
cpu-offset * cpu-nr.
|
|
|
|
- clocks : List of phandle and clock-specific pairs, one for each entry
|
|
in clock-names.
|
|
- clock-names : List of names for the GIC clock input(s). Valid clock names
|
|
depend on the GIC variant:
|
|
"ic_clk" (for "arm,arm11mp-gic")
|
|
"PERIPHCLKEN" (for "arm,cortex-a15-gic")
|
|
"PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
|
|
"clk" (for "arm,gic-400")
|
|
"gclk" (for "arm,pl390")
|
|
|
|
- power-domains : A phandle and PM domain specifier as defined by bindings of
|
|
the power controller specified by phandle, used when the GIC
|
|
is part of a Power or Clock Domain.
|
|
|
|
|
|
Example:
|
|
|
|
intc: interrupt-controller@fff11000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <1>;
|
|
interrupt-controller;
|
|
reg = <0xfff11000 0x1000>,
|
|
<0xfff10100 0x100>;
|
|
};
|
|
|
|
|
|
* GIC virtualization extensions (VGIC)
|
|
|
|
For ARM cores that support the virtualization extensions, additional
|
|
properties must be described (they only exist if the GIC is the
|
|
primary interrupt controller).
|
|
|
|
Required properties:
|
|
|
|
- reg : Additional regions specifying the base physical address and
|
|
size of the VGIC registers. The first additional region is the GIC
|
|
virtual interface control register base and size. The 2nd additional
|
|
region is the GIC virtual cpu interface register base and size.
|
|
|
|
- interrupts : VGIC maintenance interrupt.
|
|
|
|
Example:
|
|
|
|
interrupt-controller@2c001000 {
|
|
compatible = "arm,cortex-a15-gic";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x2c001000 0x1000>,
|
|
<0x2c002000 0x1000>,
|
|
<0x2c004000 0x2000>,
|
|
<0x2c006000 0x2000>;
|
|
interrupts = <1 9 0xf04>;
|
|
};
|
|
|
|
|
|
* GICv2m extension for MSI/MSI-x support (Optional)
|
|
|
|
Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
|
|
This is enabled by specifying v2m sub-node(s).
|
|
|
|
Required properties:
|
|
|
|
- compatible : The value here should contain "arm,gic-v2m-frame".
|
|
|
|
- msi-controller : Identifies the node as an MSI controller.
|
|
|
|
- reg : GICv2m MSI interface register base and size
|
|
|
|
Optional properties:
|
|
|
|
- arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
|
|
value, this property should contain the SPI base of
|
|
the MSI frame, overriding the HW value.
|
|
|
|
- arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
|
|
value, this property should contain the number of
|
|
SPIs assigned to the frame, overriding the HW value.
|
|
|
|
Example:
|
|
|
|
interrupt-controller@e1101000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-controller;
|
|
interrupts = <1 8 0xf04>;
|
|
ranges = <0 0 0 0xe1100000 0 0x100000>;
|
|
reg = <0x0 0xe1110000 0 0x01000>,
|
|
<0x0 0xe112f000 0 0x02000>,
|
|
<0x0 0xe1140000 0 0x10000>,
|
|
<0x0 0xe1160000 0 0x10000>;
|
|
v2m0: v2m@0x8000 {
|
|
compatible = "arm,gic-v2m-frame";
|
|
msi-controller;
|
|
reg = <0x0 0x80000 0 0x1000>;
|
|
};
|
|
|
|
....
|
|
|
|
v2mN: v2m@0x9000 {
|
|
compatible = "arm,gic-v2m-frame";
|
|
msi-controller;
|
|
reg = <0x0 0x90000 0 0x1000>;
|
|
};
|
|
};
|