Doug Anderson 071ff9a36c clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly ... The KDIV value is often listed as unsigned but it needs to be treated as a 16-bit signed value when using it in calculations. Fix our rate recalculation to do this correctly. Before doing this, I tried setting EPLL on exynos5250 to: rate, m, p, s, k = 80000000, 107, 2, 4, 43691 This rate is exactly from the table in the exynos5250 user manual. I read this back as 80750003 with: cat /sys/kernel/debug/clk/fin_pll/fout_epll/clk_rate After this patch, it reads back as 80000003 Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Vikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2013-06-11 09:51:26 -07:00
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clk-exynos4.c	clk: samsung: Add CLK_IGNORE_UNUSED flag for the sysreg clocks	2013-05-29 11:52:19 -07:00
clk-exynos5250.c	clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock	2013-06-10 15:14:17 -07:00
clk-exynos5440.c	clk: exynos: prepare for multiplatform	2013-04-19 23:00:38 +02:00
clk-pll.c	clk: samsung: Fix pll36xx_recalc_rate to handle kdiv properly	2013-06-11 09:51:26 -07:00
clk-pll.h
clk.c	clk: samsung: Fix compilation error	2013-04-08 23:43:12 +09:00
clk.h	clk: exynos: prepare for multiplatform	2013-04-19 23:00:38 +02:00
Makefile	clk: exynos5440: register clocks using common clock framework	2013-03-25 18:17:05 +09:00