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73e592f3bc
The tmp variable is used twice: first to pose as a register containing
a value of zero, and then to provide a temporary register that initially
is zero and get added some value. But somehow gcc decides to split those
two usages in different registers.
Example code:
u64 div64const1000(u64 x)
{
u32 y = 1000;
do_div(x, y);
return x;
}
Result:
div64const1000:
push {r4, r5, r6, r7, lr}
mov lr, #0
mov r6, r0
mov r7, r1
adr r5, .L8
ldrd r4, [r5]
mov r1, lr
umull r2, r3, r4, r6
cmn r2, r4
adcs r3, r3, r5
adc r2, lr, #0
umlal r3, r2, r5, r6
umlal r3, r1, r4, r7
mov r3, #0
adds r2, r1, r2
adc r3, r3, #0
umlal r2, r3, r5, r7
lsr r0, r2, #9
lsr r1, r3, #9
orr r0, r0, r3, lsl #23
pop {r4, r5, r6, r7, pc}
.align 3
.L8:
.word -1924145349
.word -2095944041
Full kernel build size:
text data bss dec hex filename
13663814 1553940 351368 15569122 ed90e2 vmlinux
Here the two instances of 'tmp' are assigned to r1 and lr.
To avoid that, let's mark the first 'tmp' usage in __arch_xprod_64()
with a "+r" constraint even if the register is not written to, so to
create a dependency for the second usage with the effect of enforcing
a single temporary register throughout.
Result:
div64const1000:
push {r4, r5, r6, r7}
movs r3, #0
adr r5, .L8
ldrd r4, [r5]
umull r6, r7, r4, r0
cmn r6, r4
adcs r7, r7, r5
adc r6, r3, #0
umlal r7, r6, r5, r0
umlal r7, r3, r4, r1
mov r7, #0
adds r6, r3, r6
adc r7, r7, #0
umlal r6, r7, r5, r1
lsr r0, r6, #9
lsr r1, r7, #9
orr r0, r0, r7, lsl #23
pop {r4, r5, r6, r7}
bx lr
.align 3
.L8:
.word -1924145349
.word -2095944041
text data bss dec hex filename
13663438 1553940 351368 15568746 ed8f6a vmlinux
This time 'tmp' is assigned to r3 and used throughout. However, by being
assigned to r3, that blocks usage of the r2-r3 double register slot for
64-bit values, forcing more registers to be spilled on the stack. Let's
try to help it by forcing 'tmp' to the caller-saved ip register.
Result:
div64const1000:
stmfd sp!, {r4, r5}
mov ip, #0
adr r5, .L8
ldrd r4, [r5]
umull r2, r3, r4, r0
cmn r2, r4
adcs r3, r3, r5
adc r2, ip, #0
umlal r3, r2, r5, r0
umlal r3, ip, r4, r1
mov r3, #0
adds r2, ip, r2
adc r3, r3, #0
umlal r2, r3, r5, r1
mov r0, r2, lsr #9
mov r1, r3, lsr #9
orr r0, r0, r3, asl #23
ldmfd sp!, {r4, r5}
bx lr
.align 3
.L8:
.word -1924145349
.word -2095944041
text data bss dec hex filename
13662838 1553940 351368 15568146 ed8d12 vmlinux
We could make the code marginally smaller yet by forcing 'tmp' to lr
instead, but that would have a negative inpact on branch prediction for
which "bx lr" is optimal.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
131 lines
3.1 KiB
C
131 lines
3.1 KiB
C
#ifndef __ASM_ARM_DIV64
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#define __ASM_ARM_DIV64
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#include <linux/types.h>
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#include <asm/compiler.h>
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/*
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* The semantics of __div64_32() are:
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*
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* uint32_t __div64_32(uint64_t *n, uint32_t base)
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* {
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* uint32_t remainder = *n % base;
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* *n = *n / base;
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* return remainder;
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* }
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*
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* In other words, a 64-bit dividend with a 32-bit divisor producing
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* a 64-bit result and a 32-bit remainder. To accomplish this optimally
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* we override the generic version in lib/div64.c to call our __do_div64
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* assembly implementation with completely non standard calling convention
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* for arguments and results (beware).
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*/
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#ifdef __ARMEB__
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#define __xh "r0"
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#define __xl "r1"
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#else
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#define __xl "r0"
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#define __xh "r1"
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#endif
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static inline uint32_t __div64_32(uint64_t *n, uint32_t base)
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{
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register unsigned int __base asm("r4") = base;
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register unsigned long long __n asm("r0") = *n;
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register unsigned long long __res asm("r2");
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register unsigned int __rem asm(__xh);
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asm( __asmeq("%0", __xh)
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__asmeq("%1", "r2")
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__asmeq("%2", "r0")
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__asmeq("%3", "r4")
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"bl __do_div64"
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: "=r" (__rem), "=r" (__res)
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: "r" (__n), "r" (__base)
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: "ip", "lr", "cc");
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*n = __res;
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return __rem;
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}
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#define __div64_32 __div64_32
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#if !defined(CONFIG_AEABI)
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/*
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* In OABI configurations, some uses of the do_div function
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* cause gcc to run out of registers. To work around that,
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* we can force the use of the out-of-line version for
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* configurations that build a OABI kernel.
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*/
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#define do_div(n, base) __div64_32(&(n), base)
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#else
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/*
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* gcc versions earlier than 4.0 are simply too problematic for the
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* __div64_const32() code in asm-generic/div64.h. First there is
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* gcc PR 15089 that tend to trig on more complex constructs, spurious
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* .global __udivsi3 are inserted even if none of those symbols are
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* referenced in the generated code, and those gcc versions are not able
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* to do constant propagation on long long values anyway.
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*/
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#define __div64_const32_is_OK (__GNUC__ >= 4)
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static inline uint64_t __arch_xprod_64(uint64_t m, uint64_t n, bool bias)
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{
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unsigned long long res;
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register unsigned int tmp asm("ip") = 0;
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if (!bias) {
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asm ( "umull %Q0, %R0, %Q1, %Q2\n\t"
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"mov %Q0, #0"
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: "=&r" (res)
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: "r" (m), "r" (n)
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: "cc");
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} else if (!(m & ((1ULL << 63) | (1ULL << 31)))) {
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res = m;
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asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t"
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"mov %Q0, #0"
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: "+&r" (res)
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: "r" (m), "r" (n)
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: "cc");
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} else {
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asm ( "umull %Q0, %R0, %Q2, %Q3\n\t"
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"cmn %Q0, %Q2\n\t"
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"adcs %R0, %R0, %R2\n\t"
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"adc %Q0, %1, #0"
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: "=&r" (res), "+&r" (tmp)
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: "r" (m), "r" (n)
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: "cc");
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}
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if (!(m & ((1ULL << 63) | (1ULL << 31)))) {
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asm ( "umlal %R0, %Q0, %R1, %Q2\n\t"
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"umlal %R0, %Q0, %Q1, %R2\n\t"
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"mov %R0, #0\n\t"
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"umlal %Q0, %R0, %R1, %R2"
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: "+&r" (res)
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: "r" (m), "r" (n)
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: "cc");
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} else {
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asm ( "umlal %R0, %Q0, %R2, %Q3\n\t"
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"umlal %R0, %1, %Q2, %R3\n\t"
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"mov %R0, #0\n\t"
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"adds %Q0, %1, %Q0\n\t"
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"adc %R0, %R0, #0\n\t"
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"umlal %Q0, %R0, %R2, %R3"
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: "+&r" (res), "+&r" (tmp)
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: "r" (m), "r" (n)
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: "cc");
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}
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return res;
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}
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#define __arch_xprod_64 __arch_xprod_64
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#include <asm-generic/div64.h>
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#endif
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#endif
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