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099f83aa2d
The Kconfig symbol for R10000 ll/sc errata workaround in the MIPS JIT was
misspelled, causing the workaround to not take effect when enabled.
Fixes: 72570224bb ("mips, bpf: Add JIT workarounds for CPU errata")
Reported-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20211130160824.3781635-1-johan.almbladh@anyfinetworks.com
236 lines
7.6 KiB
C
236 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Just-In-Time compiler for eBPF bytecode on 32-bit and 64-bit MIPS.
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*
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* Copyright (c) 2021 Anyfi Networks AB.
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* Author: Johan Almbladh <johan.almbladh@gmail.com>
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*
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* Based on code and ideas from
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* Copyright (c) 2017 Cavium, Inc.
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* Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>
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* Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>
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*/
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#ifndef _BPF_JIT_COMP_H
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#define _BPF_JIT_COMP_H
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/* MIPS registers */
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#define MIPS_R_ZERO 0 /* Const zero */
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#define MIPS_R_AT 1 /* Asm temp */
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#define MIPS_R_V0 2 /* Result */
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#define MIPS_R_V1 3 /* Result */
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#define MIPS_R_A0 4 /* Argument */
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#define MIPS_R_A1 5 /* Argument */
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#define MIPS_R_A2 6 /* Argument */
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#define MIPS_R_A3 7 /* Argument */
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#define MIPS_R_A4 8 /* Arg (n64) */
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#define MIPS_R_A5 9 /* Arg (n64) */
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#define MIPS_R_A6 10 /* Arg (n64) */
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#define MIPS_R_A7 11 /* Arg (n64) */
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#define MIPS_R_T0 8 /* Temp (o32) */
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#define MIPS_R_T1 9 /* Temp (o32) */
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#define MIPS_R_T2 10 /* Temp (o32) */
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#define MIPS_R_T3 11 /* Temp (o32) */
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#define MIPS_R_T4 12 /* Temporary */
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#define MIPS_R_T5 13 /* Temporary */
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#define MIPS_R_T6 14 /* Temporary */
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#define MIPS_R_T7 15 /* Temporary */
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#define MIPS_R_S0 16 /* Saved */
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#define MIPS_R_S1 17 /* Saved */
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#define MIPS_R_S2 18 /* Saved */
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#define MIPS_R_S3 19 /* Saved */
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#define MIPS_R_S4 20 /* Saved */
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#define MIPS_R_S5 21 /* Saved */
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#define MIPS_R_S6 22 /* Saved */
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#define MIPS_R_S7 23 /* Saved */
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#define MIPS_R_T8 24 /* Temporary */
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#define MIPS_R_T9 25 /* Temporary */
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/* MIPS_R_K0 26 Reserved */
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/* MIPS_R_K1 27 Reserved */
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#define MIPS_R_GP 28 /* Global ptr */
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#define MIPS_R_SP 29 /* Stack ptr */
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#define MIPS_R_FP 30 /* Frame ptr */
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#define MIPS_R_RA 31 /* Return */
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/*
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* Jump address mask for immediate jumps. The four most significant bits
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* must be equal to PC.
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*/
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#define MIPS_JMP_MASK 0x0fffffffUL
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/* Maximum number of iterations in offset table computation */
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#define JIT_MAX_ITERATIONS 8
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/*
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* Jump pseudo-instructions used internally
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* for branch conversion and branch optimization.
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*/
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#define JIT_JNSET 0xe0
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#define JIT_JNOP 0xf0
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/* Descriptor flag for PC-relative branch conversion */
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#define JIT_DESC_CONVERT BIT(31)
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/* JIT context for an eBPF program */
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struct jit_context {
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struct bpf_prog *program; /* The eBPF program being JITed */
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u32 *descriptors; /* eBPF to JITed CPU insn descriptors */
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u32 *target; /* JITed code buffer */
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u32 bpf_index; /* Index of current BPF program insn */
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u32 jit_index; /* Index of current JIT target insn */
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u32 changes; /* Number of PC-relative branch conv */
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u32 accessed; /* Bit mask of read eBPF registers */
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u32 clobbered; /* Bit mask of modified CPU registers */
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u32 stack_size; /* Total allocated stack size in bytes */
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u32 saved_size; /* Size of callee-saved registers */
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u32 stack_used; /* Stack size used for function calls */
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};
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/* Emit the instruction if the JIT memory space has been allocated */
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#define __emit(ctx, func, ...) \
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do { \
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if ((ctx)->target != NULL) { \
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u32 *p = &(ctx)->target[ctx->jit_index]; \
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uasm_i_##func(&p, ##__VA_ARGS__); \
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} \
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(ctx)->jit_index++; \
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} while (0)
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#define emit(...) __emit(__VA_ARGS__)
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/* Workaround for R10000 ll/sc errata */
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#ifdef CONFIG_WAR_R10000_LLSC
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#define LLSC_beqz beqzl
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#else
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#define LLSC_beqz beqz
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#endif
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/* Workaround for Loongson-3 ll/sc errata */
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#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
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#define LLSC_sync(ctx) emit(ctx, sync, 0)
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#define LLSC_offset 4
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#else
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#define LLSC_sync(ctx)
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#define LLSC_offset 0
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#endif
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/* Workaround for Loongson-2F jump errata */
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#ifdef CONFIG_CPU_JUMP_WORKAROUNDS
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#define JALR_MASK 0xffffffffcfffffffULL
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#else
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#define JALR_MASK (~0ULL)
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#endif
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/*
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* Mark a BPF register as accessed, it needs to be
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* initialized by the program if expected, e.g. FP.
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*/
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static inline void access_reg(struct jit_context *ctx, u8 reg)
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{
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ctx->accessed |= BIT(reg);
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}
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/*
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* Mark a CPU register as clobbered, it needs to be
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* saved/restored by the program if callee-saved.
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*/
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static inline void clobber_reg(struct jit_context *ctx, u8 reg)
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{
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ctx->clobbered |= BIT(reg);
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}
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/*
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* Push registers on the stack, starting at a given depth from the stack
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* pointer and increasing. The next depth to be written is returned.
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*/
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int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth);
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/*
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* Pop registers from the stack, starting at a given depth from the stack
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* pointer and increasing. The next depth to be read is returned.
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*/
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int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth);
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/* Compute the 28-bit jump target address from a BPF program location */
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int get_target(struct jit_context *ctx, u32 loc);
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/* Compute the PC-relative offset to relative BPF program offset */
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int get_offset(const struct jit_context *ctx, int off);
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/* dst = imm (32-bit) */
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void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm);
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/* dst = src (32-bit) */
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void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src);
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/* Validate ALU/ALU64 immediate range */
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bool valid_alu_i(u8 op, s32 imm);
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/* Rewrite ALU/ALU64 immediate operation */
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bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val);
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/* ALU immediate operation (32-bit) */
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void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op);
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/* ALU register operation (32-bit) */
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void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op);
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/* Atomic read-modify-write (32-bit) */
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void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code);
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/* Atomic compare-and-exchange (32-bit) */
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void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off);
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/* Swap bytes and truncate a register word or half word */
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void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width);
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/* Validate JMP/JMP32 immediate range */
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bool valid_jmp_i(u8 op, s32 imm);
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/* Prepare a PC-relative jump operation with immediate conditional */
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void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width,
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u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off);
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/* Prepare a PC-relative jump operation with register conditional */
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void setup_jmp_r(struct jit_context *ctx, bool same_reg,
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u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off);
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/* Finish a PC-relative jump operation */
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int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off);
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/* Conditional JMP/JMP32 immediate */
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void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op);
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/* Conditional JMP/JMP32 register */
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void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op);
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/* Jump always */
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int emit_ja(struct jit_context *ctx, s16 off);
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/* Jump to epilogue */
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int emit_exit(struct jit_context *ctx);
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/*
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* Build program prologue to set up the stack and registers.
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* This function is implemented separately for 32-bit and 64-bit JITs.
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*/
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void build_prologue(struct jit_context *ctx);
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/*
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* Build the program epilogue to restore the stack and registers.
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* This function is implemented separately for 32-bit and 64-bit JITs.
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*/
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void build_epilogue(struct jit_context *ctx, int dest_reg);
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/*
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* Convert an eBPF instruction to native instruction, i.e
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* JITs an eBPF instruction.
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* Returns :
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* 0 - Successfully JITed an 8-byte eBPF instruction
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* >0 - Successfully JITed a 16-byte eBPF instruction
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* <0 - Failed to JIT.
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* This function is implemented separately for 32-bit and 64-bit JITs.
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*/
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int build_insn(const struct bpf_insn *insn, struct jit_context *ctx);
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#endif /* _BPF_JIT_COMP_H */
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