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d900d9a435
Sample rate conversions for rates greater than 48kHz are found to be
failing. It means x->y conversions fail when either x or y is greater
than 48kHz.
This happens because, tegra210_sfc_rate_to_idx() returns incorrect
index for rates greater than 48kHz. This actually depends on the
tegra210_sfc_rates[] array and it is not in sync with frequency
values of SFC TX/RX register. To be precise, 64kHz entry is missing
in above array defined in the driver. Due to this wrong index is
returned and this results in incorrect programming of coefficients.
To fix this, align the tegra210_sfc_rates[] array with SFC register
specification and thus add 64kHz entry to it. Also, the coefficient
table is updated to reflect that none of the conversions are supported
for 64kHz.
Fixes: b2f74ec53a ("ASoC: tegra: Add Tegra210 based SFC driver")
Cc: stable@vger.kernel.org
Signed-off-by: Sheetal <sheetal@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Link: https://lore.kernel.org/r/Message-Id: <1687433656-7892-2-git-send-email-spujar@nvidia.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
79 lines
2.0 KiB
C
79 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_sfc.h - Definitions for Tegra210 SFC driver
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*
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* Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_SFC_H__
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#define __TEGRA210_SFC_H__
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/*
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* SFC_RX registers are with respect to XBAR.
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* The data comes from XBAR to SFC.
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*/
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#define TEGRA210_SFC_RX_STATUS 0x0c
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#define TEGRA210_SFC_RX_INT_STATUS 0x10
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#define TEGRA210_SFC_RX_INT_MASK 0x14
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#define TEGRA210_SFC_RX_INT_SET 0x18
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#define TEGRA210_SFC_RX_INT_CLEAR 0x1c
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#define TEGRA210_SFC_RX_CIF_CTRL 0x20
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#define TEGRA210_SFC_RX_FREQ 0x24
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/*
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* SFC_TX registers are with respect to XBAR.
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* The data goes out of SFC.
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*/
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#define TEGRA210_SFC_TX_STATUS 0x4c
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#define TEGRA210_SFC_TX_INT_STATUS 0x50
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#define TEGRA210_SFC_TX_INT_MASK 0x54
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#define TEGRA210_SFC_TX_INT_SET 0x58
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#define TEGRA210_SFC_TX_INT_CLEAR 0x5c
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#define TEGRA210_SFC_TX_CIF_CTRL 0x60
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#define TEGRA210_SFC_TX_FREQ 0x64
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/* Register offsets from TEGRA210_SFC*_BASE */
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#define TEGRA210_SFC_ENABLE 0x80
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#define TEGRA210_SFC_SOFT_RESET 0x84
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#define TEGRA210_SFC_CG 0x88
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#define TEGRA210_SFC_STATUS 0x8c
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#define TEGRA210_SFC_INT_STATUS 0x90
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#define TEGRA210_SFC_COEF_RAM 0xbc
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#define TEGRA210_SFC_CFG_RAM_CTRL 0xc0
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#define TEGRA210_SFC_CFG_RAM_DATA 0xc4
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/* Fields in TEGRA210_SFC_ENABLE */
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#define TEGRA210_SFC_EN_SHIFT 0
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#define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT)
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#define TEGRA210_SFC_NUM_RATES 13
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/* Fields in TEGRA210_SFC_COEF_RAM */
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#define TEGRA210_SFC_COEF_RAM_EN BIT(0)
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#define TEGRA210_SFC_SOFT_RESET_EN BIT(0)
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/* Coefficients */
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#define TEGRA210_SFC_COEF_RAM_DEPTH 64
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#define TEGRA210_SFC_RAM_CTRL_RW_WRITE (1 << 14)
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#define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN (1 << 13)
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#define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN (1 << 12)
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enum tegra210_sfc_path {
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SFC_RX_PATH,
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SFC_TX_PATH,
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SFC_PATHS,
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};
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struct tegra210_sfc {
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unsigned int mono_to_stereo[SFC_PATHS];
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unsigned int stereo_to_mono[SFC_PATHS];
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unsigned int srate_out;
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unsigned int srate_in;
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struct regmap *regmap;
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};
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#endif
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