mirror of
https://github.com/torvalds/linux.git
synced 2024-12-28 13:51:44 +00:00
45c3eb7d3a
Based on earlier discussions[1] we attempted to find a suitable
location for the omap DMA header in commit 2b6c4e73 (ARM: OMAP:
DMA: Move plat/dma.h to plat-omap/dma-omap.h) until the conversion
to dmaengine is complete.
Unfortunately that was before I was able to try to test compile
of the ARM multiplatform builds for omap2+, and the end result
was not very good.
So I'm creating yet another all over the place patch to cut the
last dependency for building omap2+ for ARM multiplatform. After
this, we have finally removed the driver dependencies to the
arch/arm code, except for few drivers that are being worked on.
The other option was to make the <plat-omap/dma-omap.h> path
to work, but we'd have to add some new header directory to for
multiplatform builds.
Or we would have to manually include arch/arm/plat-omap/include
again from arch/arm/Makefile for omap2+.
Neither of these alternatives sound appealing as they will
likely lead addition of various other headers exposed to the
drivers, which we want to avoid for the multiplatform kernels.
Since we already have a minimal include/linux/omap-dma.h,
let's just use that instead and add a note to it to not
use the custom omap DMA functions any longer where possible.
Note that converting omap DMA to dmaengine depends on
dmaengine supporting automatically incrementing the FIFO
address at the device end, and converting all the remaining
legacy drivers. So it's going to be few more merge windows.
[1] https://patchwork.kernel.org/patch/1519591/#
cc: Russell King <linux@arm.linux.org.uk>
cc: Kevin Hilman <khilman@ti.com>
cc: "Benoît Cousson" <b-cousson@ti.com>
cc: Herbert Xu <herbert@gondor.apana.org.au>
cc: "David S. Miller" <davem@davemloft.net>
cc: Vinod Koul <vinod.koul@intel.com>
cc: Dan Williams <djbw@fb.com>
cc: Mauro Carvalho Chehab <mchehab@infradead.org>
cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
cc: David Woodhouse <dwmw2@infradead.org>
cc: Kyungmin Park <kyungmin.park@samsung.com>
cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
cc: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
cc: Hans Verkuil <hans.verkuil@cisco.com>
cc: Vaibhav Hiremath <hvaibhav@ti.com>
cc: Lokesh Vutla <lokeshvutla@ti.com>
cc: Rusty Russell <rusty@rustcorp.com.au>
cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
cc: Afzal Mohammed <afzal@ti.com>
cc: linux-crypto@vger.kernel.org
cc: linux-media@vger.kernel.org
cc: linux-mtd@lists.infradead.org
cc: linux-usb@vger.kernel.org
cc: linux-fbdev@vger.kernel.org
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
327 lines
7.8 KiB
C
327 lines
7.8 KiB
C
/*
|
|
* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
|
|
*
|
|
* Copyright (C) 2011 Nokia Corporation
|
|
* Copyright (C) 2012 Texas Instruments, Inc.
|
|
* Paul Walmsley
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/dmaengine.h>
|
|
#include <linux/omap-dma.h>
|
|
|
|
#include "omap_hwmod.h"
|
|
#include "hdq1w.h"
|
|
|
|
#include "omap_hwmod_common_data.h"
|
|
#include "dma.h"
|
|
|
|
/* UART */
|
|
|
|
static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
|
|
.rev_offs = 0x50,
|
|
.sysc_offs = 0x54,
|
|
.syss_offs = 0x58,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
struct omap_hwmod_class omap2_uart_class = {
|
|
.name = "uart",
|
|
.sysc = &omap2_uart_sysc,
|
|
};
|
|
|
|
/*
|
|
* 'dss' class
|
|
* display sub-system
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
struct omap_hwmod_class omap2_dss_hwmod_class = {
|
|
.name = "dss",
|
|
.sysc = &omap2_dss_sysc,
|
|
.reset = omap_dss_reset,
|
|
};
|
|
|
|
/*
|
|
* 'rfbi' class
|
|
* remote frame buffer interface
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
|
|
SYSC_HAS_AUTOIDLE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
struct omap_hwmod_class omap2_rfbi_hwmod_class = {
|
|
.name = "rfbi",
|
|
.sysc = &omap2_rfbi_sysc,
|
|
};
|
|
|
|
/*
|
|
* 'venc' class
|
|
* video encoder
|
|
*/
|
|
|
|
struct omap_hwmod_class omap2_venc_hwmod_class = {
|
|
.name = "venc",
|
|
};
|
|
|
|
|
|
/* Common DMA request line data */
|
|
struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
|
|
{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
|
|
{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
|
|
{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
|
|
{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
|
|
{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
|
|
{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
|
|
{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
|
|
{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
|
|
{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
|
|
{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
|
|
{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
|
|
{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
|
|
{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
|
|
{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = 32 },
|
|
{ .name = "tx", .dma_req = 31 },
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = 34 },
|
|
{ .name = "tx", .dma_req = 33 },
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
|
|
{ .name = "rx", .dma_req = 18 },
|
|
{ .name = "tx", .dma_req = 17 },
|
|
{ .dma_req = -1 }
|
|
};
|
|
|
|
/* Other IP block data */
|
|
|
|
|
|
/*
|
|
* omap_hwmod class data
|
|
*/
|
|
|
|
struct omap_hwmod_class l3_hwmod_class = {
|
|
.name = "l3"
|
|
};
|
|
|
|
struct omap_hwmod_class l4_hwmod_class = {
|
|
.name = "l4"
|
|
};
|
|
|
|
struct omap_hwmod_class mpu_hwmod_class = {
|
|
.name = "mpu"
|
|
};
|
|
|
|
struct omap_hwmod_class iva_hwmod_class = {
|
|
.name = "iva"
|
|
};
|
|
|
|
/* Common MPU IRQ line data */
|
|
|
|
struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
|
|
{ .irq = 37 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
|
|
{ .irq = 38 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
|
|
{ .irq = 39 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
|
|
{ .irq = 40 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
|
|
{ .irq = 41 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
|
|
{ .irq = 42 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
|
|
{ .irq = 43 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
|
|
{ .irq = 44 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
|
|
{ .irq = 45 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
|
|
{ .irq = 46 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
|
|
{ .irq = 47 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
|
|
{ .irq = 72 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
|
|
{ .irq = 73 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
|
|
{ .irq = 74 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
|
|
{ .irq = 25 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
|
|
{ .irq = 56 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
|
|
{ .irq = 57 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
|
|
{ .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
|
|
{ .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
|
|
{ .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
|
|
{ .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
|
|
{ .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
|
|
{ .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
|
|
{ .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
|
|
{ .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
|
|
{ .irq = 65 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
|
|
{ .irq = 66 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|
|
struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
|
|
.rev_offs = 0x0,
|
|
.sysc_offs = 0x14,
|
|
.syss_offs = 0x18,
|
|
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
|
|
SYSS_HAS_RESET_STATUS),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
struct omap_hwmod_class omap2_hdq1w_class = {
|
|
.name = "hdq1w",
|
|
.sysc = &omap2_hdq1w_sysc,
|
|
.reset = &omap_hdq1w_reset,
|
|
};
|
|
|
|
struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
|
|
{ .irq = 58 + OMAP_INTC_START, },
|
|
{ .irq = -1 },
|
|
};
|
|
|