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bdcb2c5d5e
Field name ststus_hi should be spelled as status_hi. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
335 lines
9.7 KiB
C
335 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
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/*
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* Synopsys DesignWare AXI DMA Controller driver.
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*
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* Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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*/
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#ifndef _AXI_DMA_PLATFORM_H
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#define _AXI_DMA_PLATFORM_H
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/dmaengine.h>
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#include <linux/types.h>
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#include "../virt-dma.h"
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#define DMAC_MAX_CHANNELS 8
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#define DMAC_MAX_MASTERS 2
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#define DMAC_MAX_BLK_SIZE 0x200000
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struct dw_axi_dma_hcfg {
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u32 nr_channels;
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u32 nr_masters;
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u32 m_data_width;
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u32 block_size[DMAC_MAX_CHANNELS];
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u32 priority[DMAC_MAX_CHANNELS];
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/* maximum supported axi burst length */
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u32 axi_rw_burst_len;
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bool restrict_axi_burst_len;
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};
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struct axi_dma_chan {
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struct axi_dma_chip *chip;
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void __iomem *chan_regs;
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u8 id;
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atomic_t descs_allocated;
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struct virt_dma_chan vc;
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/* these other elements are all protected by vc.lock */
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bool is_paused;
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};
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struct dw_axi_dma {
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struct dma_device dma;
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struct dw_axi_dma_hcfg *hdata;
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struct dma_pool *desc_pool;
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/* channels */
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struct axi_dma_chan *chan;
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};
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struct axi_dma_chip {
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struct device *dev;
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int irq;
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void __iomem *regs;
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struct clk *core_clk;
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struct clk *cfgr_clk;
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struct dw_axi_dma *dw;
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};
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/* LLI == Linked List Item */
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struct __packed axi_dma_lli {
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__le64 sar;
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__le64 dar;
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__le32 block_ts_lo;
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__le32 block_ts_hi;
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__le64 llp;
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__le32 ctl_lo;
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__le32 ctl_hi;
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__le32 sstat;
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__le32 dstat;
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__le32 status_lo;
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__le32 status_hi;
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__le32 reserved_lo;
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__le32 reserved_hi;
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};
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struct axi_dma_desc {
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struct axi_dma_lli lli;
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struct virt_dma_desc vd;
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struct axi_dma_chan *chan;
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struct list_head xfer_list;
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};
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static inline struct device *dchan2dev(struct dma_chan *dchan)
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{
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return &dchan->dev->device;
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}
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static inline struct device *chan2dev(struct axi_dma_chan *chan)
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{
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return &chan->vc.chan.dev->device;
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}
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static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd)
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{
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return container_of(vd, struct axi_dma_desc, vd);
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}
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static inline struct axi_dma_chan *vc_to_axi_dma_chan(struct virt_dma_chan *vc)
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{
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return container_of(vc, struct axi_dma_chan, vc);
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}
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static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
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{
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return vc_to_axi_dma_chan(to_virt_chan(dchan));
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}
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#define COMMON_REG_LEN 0x100
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#define CHAN_REG_LEN 0x100
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/* Common registers offset */
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#define DMAC_ID 0x000 /* R DMAC ID */
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#define DMAC_COMPVER 0x008 /* R DMAC Component Version */
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#define DMAC_CFG 0x010 /* R/W DMAC Configuration */
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#define DMAC_CHEN 0x018 /* R/W DMAC Channel Enable */
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#define DMAC_CHEN_L 0x018 /* R/W DMAC Channel Enable 00-31 */
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#define DMAC_CHEN_H 0x01C /* R/W DMAC Channel Enable 32-63 */
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#define DMAC_INTSTATUS 0x030 /* R DMAC Interrupt Status */
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#define DMAC_COMMON_INTCLEAR 0x038 /* W DMAC Interrupt Clear */
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#define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
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#define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
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#define DMAC_COMMON_INTSTATUS 0x050 /* R DMAC Interrupt Status */
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#define DMAC_RESET 0x058 /* R DMAC Reset Register1 */
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/* DMA channel registers offset */
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#define CH_SAR 0x000 /* R/W Chan Source Address */
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#define CH_DAR 0x008 /* R/W Chan Destination Address */
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#define CH_BLOCK_TS 0x010 /* R/W Chan Block Transfer Size */
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#define CH_CTL 0x018 /* R/W Chan Control */
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#define CH_CTL_L 0x018 /* R/W Chan Control 00-31 */
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#define CH_CTL_H 0x01C /* R/W Chan Control 32-63 */
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#define CH_CFG 0x020 /* R/W Chan Configuration */
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#define CH_CFG_L 0x020 /* R/W Chan Configuration 00-31 */
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#define CH_CFG_H 0x024 /* R/W Chan Configuration 32-63 */
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#define CH_LLP 0x028 /* R/W Chan Linked List Pointer */
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#define CH_STATUS 0x030 /* R Chan Status */
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#define CH_SWHSSRC 0x038 /* R/W Chan SW Handshake Source */
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#define CH_SWHSDST 0x040 /* R/W Chan SW Handshake Destination */
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#define CH_BLK_TFR_RESUMEREQ 0x048 /* W Chan Block Transfer Resume Req */
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#define CH_AXI_ID 0x050 /* R/W Chan AXI ID */
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#define CH_AXI_QOS 0x058 /* R/W Chan AXI QOS */
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#define CH_SSTAT 0x060 /* R Chan Source Status */
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#define CH_DSTAT 0x068 /* R Chan Destination Status */
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#define CH_SSTATAR 0x070 /* R/W Chan Source Status Fetch Addr */
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#define CH_DSTATAR 0x078 /* R/W Chan Destination Status Fetch Addr */
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#define CH_INTSTATUS_ENA 0x080 /* R/W Chan Interrupt Status Enable */
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#define CH_INTSTATUS 0x088 /* R/W Chan Interrupt Status */
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#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
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#define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
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/* DMAC_CFG */
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#define DMAC_EN_POS 0
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#define DMAC_EN_MASK BIT(DMAC_EN_POS)
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#define INT_EN_POS 1
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#define INT_EN_MASK BIT(INT_EN_POS)
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#define DMAC_CHAN_EN_SHIFT 0
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#define DMAC_CHAN_EN_WE_SHIFT 8
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#define DMAC_CHAN_SUSP_SHIFT 16
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#define DMAC_CHAN_SUSP_WE_SHIFT 24
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/* CH_CTL_H */
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#define CH_CTL_H_ARLEN_EN BIT(6)
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#define CH_CTL_H_ARLEN_POS 7
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#define CH_CTL_H_AWLEN_EN BIT(15)
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#define CH_CTL_H_AWLEN_POS 16
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enum {
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DWAXIDMAC_ARWLEN_1 = 0,
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DWAXIDMAC_ARWLEN_2 = 1,
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DWAXIDMAC_ARWLEN_4 = 3,
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DWAXIDMAC_ARWLEN_8 = 7,
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DWAXIDMAC_ARWLEN_16 = 15,
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DWAXIDMAC_ARWLEN_32 = 31,
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DWAXIDMAC_ARWLEN_64 = 63,
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DWAXIDMAC_ARWLEN_128 = 127,
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DWAXIDMAC_ARWLEN_256 = 255,
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DWAXIDMAC_ARWLEN_MIN = DWAXIDMAC_ARWLEN_1,
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DWAXIDMAC_ARWLEN_MAX = DWAXIDMAC_ARWLEN_256
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};
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#define CH_CTL_H_LLI_LAST BIT(30)
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#define CH_CTL_H_LLI_VALID BIT(31)
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/* CH_CTL_L */
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#define CH_CTL_L_LAST_WRITE_EN BIT(30)
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#define CH_CTL_L_DST_MSIZE_POS 18
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#define CH_CTL_L_SRC_MSIZE_POS 14
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enum {
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DWAXIDMAC_BURST_TRANS_LEN_1 = 0,
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DWAXIDMAC_BURST_TRANS_LEN_4,
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DWAXIDMAC_BURST_TRANS_LEN_8,
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DWAXIDMAC_BURST_TRANS_LEN_16,
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DWAXIDMAC_BURST_TRANS_LEN_32,
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DWAXIDMAC_BURST_TRANS_LEN_64,
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DWAXIDMAC_BURST_TRANS_LEN_128,
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DWAXIDMAC_BURST_TRANS_LEN_256,
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DWAXIDMAC_BURST_TRANS_LEN_512,
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DWAXIDMAC_BURST_TRANS_LEN_1024
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};
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#define CH_CTL_L_DST_WIDTH_POS 11
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#define CH_CTL_L_SRC_WIDTH_POS 8
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#define CH_CTL_L_DST_INC_POS 6
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#define CH_CTL_L_SRC_INC_POS 4
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enum {
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DWAXIDMAC_CH_CTL_L_INC = 0,
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DWAXIDMAC_CH_CTL_L_NOINC
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};
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#define CH_CTL_L_DST_MAST BIT(2)
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#define CH_CTL_L_SRC_MAST BIT(0)
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/* CH_CFG_H */
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#define CH_CFG_H_PRIORITY_POS 17
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#define CH_CFG_H_HS_SEL_DST_POS 4
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#define CH_CFG_H_HS_SEL_SRC_POS 3
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enum {
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DWAXIDMAC_HS_SEL_HW = 0,
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DWAXIDMAC_HS_SEL_SW
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};
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#define CH_CFG_H_TT_FC_POS 0
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enum {
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DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0,
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DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC,
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DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC,
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DWAXIDMAC_TT_FC_PER_TO_PER_DMAC,
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DWAXIDMAC_TT_FC_PER_TO_MEM_SRC,
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DWAXIDMAC_TT_FC_PER_TO_PER_SRC,
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DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
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DWAXIDMAC_TT_FC_PER_TO_PER_DST
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};
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/* CH_CFG_L */
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#define CH_CFG_L_DST_MULTBLK_TYPE_POS 2
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#define CH_CFG_L_SRC_MULTBLK_TYPE_POS 0
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enum {
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DWAXIDMAC_MBLK_TYPE_CONTIGUOUS = 0,
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DWAXIDMAC_MBLK_TYPE_RELOAD,
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DWAXIDMAC_MBLK_TYPE_SHADOW_REG,
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DWAXIDMAC_MBLK_TYPE_LL
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};
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/**
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* DW AXI DMA channel interrupts
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*
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* @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt
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* @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete
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* @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
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* @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete
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* @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete
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* @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error
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* @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error
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* @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error
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* @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error
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* @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error
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* @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error
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* @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error
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* @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error
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* @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error
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* @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error
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* @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error
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* @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
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* @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
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* @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
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* @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error
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* @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error
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* @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status
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* @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status
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* @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
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* @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
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* @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status
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* @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts
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* @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts
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*/
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enum {
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DWAXIDMAC_IRQ_NONE = 0,
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DWAXIDMAC_IRQ_BLOCK_TRF = BIT(0),
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DWAXIDMAC_IRQ_DMA_TRF = BIT(1),
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DWAXIDMAC_IRQ_SRC_TRAN = BIT(3),
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DWAXIDMAC_IRQ_DST_TRAN = BIT(4),
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DWAXIDMAC_IRQ_SRC_DEC_ERR = BIT(5),
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DWAXIDMAC_IRQ_DST_DEC_ERR = BIT(6),
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DWAXIDMAC_IRQ_SRC_SLV_ERR = BIT(7),
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DWAXIDMAC_IRQ_DST_SLV_ERR = BIT(8),
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DWAXIDMAC_IRQ_LLI_RD_DEC_ERR = BIT(9),
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DWAXIDMAC_IRQ_LLI_WR_DEC_ERR = BIT(10),
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DWAXIDMAC_IRQ_LLI_RD_SLV_ERR = BIT(11),
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DWAXIDMAC_IRQ_LLI_WR_SLV_ERR = BIT(12),
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DWAXIDMAC_IRQ_INVALID_ERR = BIT(13),
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DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR = BIT(14),
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DWAXIDMAC_IRQ_DEC_ERR = BIT(16),
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DWAXIDMAC_IRQ_WR2RO_ERR = BIT(17),
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DWAXIDMAC_IRQ_RD2RWO_ERR = BIT(18),
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DWAXIDMAC_IRQ_WRONCHEN_ERR = BIT(19),
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DWAXIDMAC_IRQ_SHADOWREG_ERR = BIT(20),
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DWAXIDMAC_IRQ_WRONHOLD_ERR = BIT(21),
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DWAXIDMAC_IRQ_LOCK_CLEARED = BIT(27),
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DWAXIDMAC_IRQ_SRC_SUSPENDED = BIT(28),
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DWAXIDMAC_IRQ_SUSPENDED = BIT(29),
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DWAXIDMAC_IRQ_DISABLED = BIT(30),
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DWAXIDMAC_IRQ_ABORTED = BIT(31),
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DWAXIDMAC_IRQ_ALL_ERR = (GENMASK(21, 16) | GENMASK(14, 5)),
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DWAXIDMAC_IRQ_ALL = GENMASK(31, 0)
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};
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enum {
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DWAXIDMAC_TRANS_WIDTH_8 = 0,
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DWAXIDMAC_TRANS_WIDTH_16,
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DWAXIDMAC_TRANS_WIDTH_32,
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DWAXIDMAC_TRANS_WIDTH_64,
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DWAXIDMAC_TRANS_WIDTH_128,
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DWAXIDMAC_TRANS_WIDTH_256,
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DWAXIDMAC_TRANS_WIDTH_512,
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DWAXIDMAC_TRANS_WIDTH_MAX = DWAXIDMAC_TRANS_WIDTH_512
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};
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#endif /* _AXI_DMA_PLATFORM_H */
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