mirror of
https://github.com/torvalds/linux.git
synced 2024-12-25 12:21:37 +00:00
0585a155a7
This patch adds pcie nodes to the appropriate dts files, plus adds some probing code for the boards. Also, remove of_device_is_avaliable() check from the mpc837x_mds.c board file, as mpc83xx_add_bridge() has the same check now. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
417 lines
9.6 KiB
Plaintext
417 lines
9.6 KiB
Plaintext
/*
|
|
* MPC8315E RDB Device Tree Source
|
|
*
|
|
* Copyright 2007 Freescale Semiconductor Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
compatible = "fsl,mpc8315erdb";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
aliases {
|
|
ethernet0 = &enet0;
|
|
ethernet1 = &enet1;
|
|
serial0 = &serial0;
|
|
serial1 = &serial1;
|
|
pci0 = &pci0;
|
|
pci1 = &pci1;
|
|
pci2 = &pci2;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
PowerPC,8315@0 {
|
|
device_type = "cpu";
|
|
reg = <0x0>;
|
|
d-cache-line-size = <32>;
|
|
i-cache-line-size = <32>;
|
|
d-cache-size = <16384>;
|
|
i-cache-size = <16384>;
|
|
timebase-frequency = <0>; // from bootloader
|
|
bus-frequency = <0>; // from bootloader
|
|
clock-frequency = <0>; // from bootloader
|
|
};
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x08000000>; // 128MB at 0
|
|
};
|
|
|
|
localbus@e0005000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
|
|
reg = <0xe0005000 0x1000>;
|
|
interrupts = <77 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
|
|
// CS0 and CS1 are swapped when
|
|
// booting from nand, but the
|
|
// addresses are the same.
|
|
ranges = <0x0 0x0 0xfe000000 0x00800000
|
|
0x1 0x0 0xe0600000 0x00002000
|
|
0x2 0x0 0xf0000000 0x00020000
|
|
0x3 0x0 0xfa000000 0x00008000>;
|
|
|
|
flash@0,0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "cfi-flash";
|
|
reg = <0x0 0x0 0x800000>;
|
|
bank-width = <2>;
|
|
device-width = <1>;
|
|
};
|
|
|
|
nand@1,0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,mpc8315-fcm-nand",
|
|
"fsl,elbc-fcm-nand";
|
|
reg = <0x1 0x0 0x2000>;
|
|
|
|
u-boot@0 {
|
|
reg = <0x0 0x100000>;
|
|
read-only;
|
|
};
|
|
|
|
kernel@100000 {
|
|
reg = <0x100000 0x300000>;
|
|
};
|
|
fs@400000 {
|
|
reg = <0x400000 0x1c00000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
immr@e0000000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "fsl,mpc8315-immr", "simple-bus";
|
|
ranges = <0 0xe0000000 0x00100000>;
|
|
reg = <0xe0000000 0x00000200>;
|
|
bus-frequency = <0>;
|
|
|
|
wdt@200 {
|
|
device_type = "watchdog";
|
|
compatible = "mpc83xx_wdt";
|
|
reg = <0x200 0x100>;
|
|
};
|
|
|
|
i2c@3000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
compatible = "fsl-i2c";
|
|
reg = <0x3000 0x100>;
|
|
interrupts = <14 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
dfsrr;
|
|
rtc@68 {
|
|
compatible = "dallas,ds1339";
|
|
reg = <0x68>;
|
|
};
|
|
|
|
mcu_pio: mcu@a {
|
|
#gpio-cells = <2>;
|
|
compatible = "fsl,mc9s08qg8-mpc8315erdb",
|
|
"fsl,mcu-mpc8349emitx";
|
|
reg = <0x0a>;
|
|
gpio-controller;
|
|
};
|
|
};
|
|
|
|
spi@7000 {
|
|
cell-index = <0>;
|
|
compatible = "fsl,spi";
|
|
reg = <0x7000 0x1000>;
|
|
interrupts = <16 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
mode = "cpu";
|
|
};
|
|
|
|
dma@82a8 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,mpc8315-dma", "fsl,elo-dma";
|
|
reg = <0x82a8 4>;
|
|
ranges = <0 0x8100 0x1a8>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
cell-index = <0>;
|
|
dma-channel@0 {
|
|
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
|
|
reg = <0 0x80>;
|
|
cell-index = <0>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
};
|
|
dma-channel@80 {
|
|
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
|
|
reg = <0x80 0x80>;
|
|
cell-index = <1>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
};
|
|
dma-channel@100 {
|
|
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
|
|
reg = <0x100 0x80>;
|
|
cell-index = <2>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
};
|
|
dma-channel@180 {
|
|
compatible = "fsl,mpc8315-dma-channel", "fsl,elo-dma-channel";
|
|
reg = <0x180 0x28>;
|
|
cell-index = <3>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <71 8>;
|
|
};
|
|
};
|
|
|
|
usb@23000 {
|
|
compatible = "fsl-usb2-dr";
|
|
reg = <0x23000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <38 0x8>;
|
|
phy_type = "utmi";
|
|
};
|
|
|
|
mdio@24520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-mdio";
|
|
reg = <0x24520 0x20>;
|
|
phy0: ethernet-phy@0 {
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <20 0x8>;
|
|
reg = <0x0>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
phy1: ethernet-phy@1 {
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <19 0x8>;
|
|
reg = <0x1>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
tbi0: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
|
|
mdio@25520 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,gianfar-tbi";
|
|
reg = <0x25520 0x20>;
|
|
|
|
tbi1: tbi-phy@11 {
|
|
reg = <0x11>;
|
|
device_type = "tbi-phy";
|
|
};
|
|
};
|
|
|
|
|
|
enet0: ethernet@24000 {
|
|
cell-index = <0>;
|
|
device_type = "network";
|
|
model = "eTSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x24000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <32 0x8 33 0x8 34 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
tbi-handle = <&tbi0>;
|
|
phy-handle = < &phy0 >;
|
|
};
|
|
|
|
enet1: ethernet@25000 {
|
|
cell-index = <1>;
|
|
device_type = "network";
|
|
model = "eTSEC";
|
|
compatible = "gianfar";
|
|
reg = <0x25000 0x1000>;
|
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
|
interrupts = <35 0x8 36 0x8 37 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
tbi-handle = <&tbi1>;
|
|
phy-handle = < &phy1 >;
|
|
};
|
|
|
|
serial0: serial@4500 {
|
|
cell-index = <0>;
|
|
device_type = "serial";
|
|
compatible = "ns16550";
|
|
reg = <0x4500 0x100>;
|
|
clock-frequency = <133333333>;
|
|
interrupts = <9 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
};
|
|
|
|
serial1: serial@4600 {
|
|
cell-index = <1>;
|
|
device_type = "serial";
|
|
compatible = "ns16550";
|
|
reg = <0x4600 0x100>;
|
|
clock-frequency = <133333333>;
|
|
interrupts = <10 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
};
|
|
|
|
crypto@30000 {
|
|
compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
|
|
"fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
|
|
"fsl,sec2.0";
|
|
reg = <0x30000 0x10000>;
|
|
interrupts = <11 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
fsl,num-channels = <4>;
|
|
fsl,channel-fifo-len = <24>;
|
|
fsl,exec-units-mask = <0x97c>;
|
|
fsl,descriptor-types-mask = <0x3ab0abf>;
|
|
};
|
|
|
|
sata@18000 {
|
|
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
|
|
reg = <0x18000 0x1000>;
|
|
cell-index = <1>;
|
|
interrupts = <44 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
};
|
|
|
|
sata@19000 {
|
|
compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
|
|
reg = <0x19000 0x1000>;
|
|
cell-index = <2>;
|
|
interrupts = <45 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
};
|
|
|
|
/* IPIC
|
|
* interrupts cell = <intr #, sense>
|
|
* sense values match linux IORESOURCE_IRQ_* defines:
|
|
* sense == 8: Level, low assertion
|
|
* sense == 2: Edge, high-to-low change
|
|
*/
|
|
ipic: interrupt-controller@700 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x700 0x100>;
|
|
device_type = "ipic";
|
|
};
|
|
};
|
|
|
|
pci0: pci@e0008500 {
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0E -mini PCI */
|
|
0x7000 0x0 0x0 0x1 &ipic 18 0x8
|
|
0x7000 0x0 0x0 0x2 &ipic 18 0x8
|
|
0x7000 0x0 0x0 0x3 &ipic 18 0x8
|
|
0x7000 0x0 0x0 0x4 &ipic 18 0x8
|
|
|
|
/* IDSEL 0x0F -mini PCI */
|
|
0x7800 0x0 0x0 0x1 &ipic 17 0x8
|
|
0x7800 0x0 0x0 0x2 &ipic 17 0x8
|
|
0x7800 0x0 0x0 0x3 &ipic 17 0x8
|
|
0x7800 0x0 0x0 0x4 &ipic 17 0x8
|
|
|
|
/* IDSEL 0x10 - PCI slot */
|
|
0x8000 0x0 0x0 0x1 &ipic 48 0x8
|
|
0x8000 0x0 0x0 0x2 &ipic 17 0x8
|
|
0x8000 0x0 0x0 0x3 &ipic 48 0x8
|
|
0x8000 0x0 0x0 0x4 &ipic 17 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
interrupts = <66 0x8>;
|
|
bus-range = <0x0 0x0>;
|
|
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
|
0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
|
0x01000000 0 0x00000000 0xe0300000 0 0x00100000>;
|
|
clock-frequency = <66666666>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xe0008500 0x100 /* internal registers */
|
|
0xe0008300 0x8>; /* config space access registers */
|
|
compatible = "fsl,mpc8349-pci";
|
|
device_type = "pci";
|
|
};
|
|
|
|
pci1: pcie@e0009000 {
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
|
|
reg = <0xe0009000 0x00001000>;
|
|
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
|
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
|
|
bus-range = <0 255>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &ipic 1 8
|
|
0 0 0 2 &ipic 1 8
|
|
0 0 0 3 &ipic 1 8
|
|
0 0 0 4 &ipic 1 8>;
|
|
clock-frequency = <0>;
|
|
|
|
pcie@0 {
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
reg = <0 0 0 0 0>;
|
|
ranges = <0x02000000 0 0xa0000000
|
|
0x02000000 0 0xa0000000
|
|
0 0x10000000
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0x00000000
|
|
0 0x00800000>;
|
|
};
|
|
};
|
|
|
|
pci2: pcie@e000a000 {
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
|
|
reg = <0xe000a000 0x00001000>;
|
|
ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
|
|
0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
|
|
bus-range = <0 255>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &ipic 2 8
|
|
0 0 0 2 &ipic 2 8
|
|
0 0 0 3 &ipic 2 8
|
|
0 0 0 4 &ipic 2 8>;
|
|
clock-frequency = <0>;
|
|
|
|
pcie@0 {
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
reg = <0 0 0 0 0>;
|
|
ranges = <0x02000000 0 0xc0000000
|
|
0x02000000 0 0xc0000000
|
|
0 0x10000000
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0x00000000
|
|
0 0x00800000>;
|
|
};
|
|
};
|
|
};
|