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b85a3ef4ac
The 1st board support is minimal to get a system up and running on the Xilinx platform. This platform reuses the clock implementation from plat-versatile, and it depends entirely on CONFIG_OF support. There is only one board support file which obtains all device information from a device tree dtb file which is passed to the kernel at boot time. Signed-off-by: John Linn <john.linn@xilinx.com>
299 lines
8.8 KiB
C
299 lines
8.8 KiB
C
/*
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* This file contains driver for the Xilinx PS Timer Counter IP.
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*
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* Copyright (C) 2011 Xilinx
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*
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* based on arch/mips/kernel/time.c timer driver
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/mach/time.h>
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#include <mach/zynq_soc.h>
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#include "common.h"
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#define IRQ_TIMERCOUNTER0 42
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/*
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* This driver configures the 2 16-bit count-up timers as follows:
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*
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* T1: Timer 1, clocksource for generic timekeeping
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* T2: Timer 2, clockevent source for hrtimers
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* T3: Timer 3, <unused>
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*
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* The input frequency to the timer module for emulation is 2.5MHz which is
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* common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
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* the timers are clocked at 78.125KHz (12.8 us resolution).
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*
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* The input frequency to the timer module in silicon will be 200MHz. With the
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* pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
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*/
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#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
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#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
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#define XTTCPSS_TIMER_BASE TTC0_BASE
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#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
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/*
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* Timer Register Offset Definitions of Timer 1, Increment base address by 4
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* and use same offsets for Timer 2
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*/
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#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
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#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
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#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
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#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
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#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */
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#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */
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#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */
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#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
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#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
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#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
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/* Setup the timers to use pre-scaling */
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#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32)
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/**
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* struct xttcpss_timer - This definition defines local timer structure
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*
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* @base_addr: Base address of timer
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**/
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struct xttcpss_timer {
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void __iomem *base_addr;
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};
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static struct xttcpss_timer timers[2];
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static struct clock_event_device xttcpss_clockevent;
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/**
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* xttcpss_set_interval - Set the timer interval value
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*
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* @timer: Pointer to the timer instance
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* @cycles: Timer interval ticks
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**/
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static void xttcpss_set_interval(struct xttcpss_timer *timer,
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unsigned long cycles)
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{
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u32 ctrl_reg;
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/* Disable the counter, set the counter value and re-enable counter */
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ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
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ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
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__raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
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/* Reset the counter (0x10) so that it starts from 0, one-shot
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mode makes this needed for timing to be right. */
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ctrl_reg |= 0x10;
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ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
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}
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/**
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* xttcpss_clock_event_interrupt - Clock event timer interrupt handler
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*
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* @irq: IRQ number of the Timer
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* @dev_id: void pointer to the xttcpss_timer instance
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*
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* returns: Always IRQ_HANDLED - success
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**/
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static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &xttcpss_clockevent;
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struct xttcpss_timer *timer = dev_id;
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/* Acknowledge the interrupt and call event handler */
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__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
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timer->base_addr + XTTCPSS_ISR_OFFSET);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction event_timer_irq = {
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.name = "xttcpss clockevent",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = xttcpss_clock_event_interrupt,
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};
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/**
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* xttcpss_timer_hardware_init - Initialize the timer hardware
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*
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* Initialize the hardware to start the clock source, get the clock
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* event timer ready to use, and hook up the interrupt.
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**/
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static void __init xttcpss_timer_hardware_init(void)
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{
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/* Setup the clock source counter to be an incrementing counter
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* with no interrupt and it rolls over at 0xFFFF. Pre-scale
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it by 32 also. Let it start running now.
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*/
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timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
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__raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
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XTTCPSS_IER_OFFSET);
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__raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
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XTTCPSS_CLK_CNTRL_OFFSET);
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__raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
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XTTCPSS_CNT_CNTRL_OFFSET);
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/* Setup the clock event timer to be an interval timer which
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* is prescaled by 32 using the interval interrupt. Leave it
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* disabled for now.
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*/
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timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
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__raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
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XTTCPSS_CNT_CNTRL_OFFSET);
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__raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
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XTTCPSS_CLK_CNTRL_OFFSET);
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__raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
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XTTCPSS_IER_OFFSET);
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/* Setup IRQ the clock event timer */
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event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
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setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
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}
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/**
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* __raw_readl_cycles - Reads the timer counter register
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*
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* returns: Current timer counter register value
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**/
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static cycle_t __raw_readl_cycles(struct clocksource *cs)
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{
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struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
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return (cycle_t)__raw_readl(timer->base_addr +
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XTTCPSS_COUNT_VAL_OFFSET);
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}
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/*
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* Instantiate and initialize the clock source structure
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*/
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static struct clocksource clocksource_xttcpss = {
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.name = "xttcpss_timer1",
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.rating = 200, /* Reasonable clock source */
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.read = __raw_readl_cycles,
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.mask = CLOCKSOURCE_MASK(16),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/**
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* xttcpss_set_next_event - Sets the time interval for next event
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*
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* @cycles: Timer interval ticks
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* @evt: Address of clock event instance
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*
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* returns: Always 0 - success
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**/
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static int xttcpss_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
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xttcpss_set_interval(timer, cycles);
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return 0;
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}
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/**
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* xttcpss_set_mode - Sets the mode of timer
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*
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* @mode: Mode to be set
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* @evt: Address of clock event instance
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**/
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static void xttcpss_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
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u32 ctrl_reg;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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xttcpss_set_interval(timer, TIMER_RATE / HZ);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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ctrl_reg = __raw_readl(timer->base_addr +
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XTTCPSS_CNT_CNTRL_OFFSET);
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ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg,
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timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
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break;
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case CLOCK_EVT_MODE_RESUME:
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ctrl_reg = __raw_readl(timer->base_addr +
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XTTCPSS_CNT_CNTRL_OFFSET);
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ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg,
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timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
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break;
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}
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}
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/*
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* Instantiate and initialize the clock event structure
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*/
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static struct clock_event_device xttcpss_clockevent = {
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.name = "xttcpss_timer2",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = xttcpss_set_next_event,
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.set_mode = xttcpss_set_mode,
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.rating = 200,
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};
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/**
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* xttcpss_timer_init - Initialize the timer
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*
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* Initializes the timer hardware and register the clock source and clock event
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* timers with Linux kernal timer framework
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**/
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static void __init xttcpss_timer_init(void)
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{
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xttcpss_timer_hardware_init();
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clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE);
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/* Calculate the parameters to allow the clockevent to operate using
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integer math
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*/
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clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4);
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xttcpss_clockevent.max_delta_ns =
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clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
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xttcpss_clockevent.min_delta_ns =
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clockevent_delta2ns(1, &xttcpss_clockevent);
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/* Indicate that clock event is on 1st CPU as SMP boot needs it */
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xttcpss_clockevent.cpumask = cpumask_of(0);
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clockevents_register_device(&xttcpss_clockevent);
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}
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/*
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* Instantiate and initialize the system timer structure
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*/
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struct sys_timer xttcpss_sys_timer = {
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.init = xttcpss_timer_init,
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};
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