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af873fcece
Based on 1 normalized pattern(s): license terms gnu general public license gpl version 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
262 lines
7.4 KiB
C
262 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* VIA Chipset Watchdog Driver
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*
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* Copyright (C) 2011 Sigfox
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* Author: Marc Vertes <marc.vertes@sigfox.com>
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* Based on a preliminary version from Harald Welte <HaraldWelte@viatech.com>
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* Timer code by Wim Van Sebroeck <wim@iguana.be>
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*
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* Caveat: PnP must be enabled in BIOS to allow full access to watchdog
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* control registers. If not, the watchdog must be configured in BIOS manually.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/timer.h>
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#include <linux/watchdog.h>
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/* Configuration registers relative to the pci device */
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#define VIA_WDT_MMIO_BASE 0xe8 /* MMIO region base address */
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#define VIA_WDT_CONF 0xec /* watchdog enable state */
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/* Relevant bits for the VIA_WDT_CONF register */
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#define VIA_WDT_CONF_ENABLE 0x01 /* 1: enable watchdog */
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#define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
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/*
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* The MMIO region contains the watchdog control register and the
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* hardware timer counter.
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*/
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#define VIA_WDT_MMIO_LEN 8 /* MMIO region length in bytes */
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#define VIA_WDT_CTL 0 /* MMIO addr+0: state/control reg. */
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#define VIA_WDT_COUNT 4 /* MMIO addr+4: timer counter reg. */
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/* Bits for the VIA_WDT_CTL register */
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#define VIA_WDT_RUNNING 0x01 /* 0: stop, 1: running */
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#define VIA_WDT_FIRED 0x02 /* 1: restarted by expired watchdog */
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#define VIA_WDT_PWROFF 0x04 /* 0: reset, 1: poweroff */
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#define VIA_WDT_DISABLED 0x08 /* 1: timer is disabled */
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#define VIA_WDT_TRIGGER 0x80 /* 1: start a new countdown */
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/* Hardware heartbeat in seconds */
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#define WDT_HW_HEARTBEAT 1
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/* Timer heartbeat (500ms) */
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#define WDT_HEARTBEAT (HZ/2) /* should be <= ((WDT_HW_HEARTBEAT*HZ)/2) */
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/* User space timeout in seconds */
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#define WDT_TIMEOUT_MAX 1023 /* approx. 17 min. */
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#define WDT_TIMEOUT 60
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static int timeout = WDT_TIMEOUT;
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module_param(timeout, int, 0);
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MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, between 1 and 1023 "
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"(default = " __MODULE_STRING(WDT_TIMEOUT) ")");
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
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"(default = " __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static struct watchdog_device wdt_dev;
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static struct resource wdt_res;
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static void __iomem *wdt_mem;
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static unsigned int mmio;
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static void wdt_timer_tick(struct timer_list *unused);
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static DEFINE_TIMER(timer, wdt_timer_tick);
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/* The timer that pings the watchdog */
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static unsigned long next_heartbeat; /* the next_heartbeat for the timer */
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static inline void wdt_reset(void)
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{
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unsigned int ctl = readl(wdt_mem);
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writel(ctl | VIA_WDT_TRIGGER, wdt_mem);
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}
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/*
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* Timer tick: the timer will make sure that the watchdog timer hardware
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* is being reset in time. The conditions to do this are:
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* 1) the watchdog timer has been started and /dev/watchdog is open
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* and there is still time left before userspace should send the
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* next heartbeat/ping. (note: the internal heartbeat is much smaller
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* then the external/userspace heartbeat).
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* 2) the watchdog timer has been stopped by userspace.
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*/
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static void wdt_timer_tick(struct timer_list *unused)
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{
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if (time_before(jiffies, next_heartbeat) ||
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(!watchdog_active(&wdt_dev))) {
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wdt_reset();
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mod_timer(&timer, jiffies + WDT_HEARTBEAT);
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} else
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pr_crit("I will reboot your machine !\n");
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}
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static int wdt_ping(struct watchdog_device *wdd)
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{
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/* calculate when the next userspace timeout will be */
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next_heartbeat = jiffies + wdd->timeout * HZ;
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return 0;
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}
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static int wdt_start(struct watchdog_device *wdd)
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{
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unsigned int ctl = readl(wdt_mem);
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writel(wdd->timeout, wdt_mem + VIA_WDT_COUNT);
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writel(ctl | VIA_WDT_RUNNING | VIA_WDT_TRIGGER, wdt_mem);
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wdt_ping(wdd);
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mod_timer(&timer, jiffies + WDT_HEARTBEAT);
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return 0;
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}
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static int wdt_stop(struct watchdog_device *wdd)
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{
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unsigned int ctl = readl(wdt_mem);
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writel(ctl & ~VIA_WDT_RUNNING, wdt_mem);
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return 0;
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}
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static int wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int new_timeout)
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{
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writel(new_timeout, wdt_mem + VIA_WDT_COUNT);
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wdd->timeout = new_timeout;
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return 0;
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}
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static const struct watchdog_info wdt_info = {
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.identity = "VIA watchdog",
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.options = WDIOF_CARDRESET |
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WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING,
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};
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static const struct watchdog_ops wdt_ops = {
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.owner = THIS_MODULE,
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.start = wdt_start,
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.stop = wdt_stop,
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.ping = wdt_ping,
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.set_timeout = wdt_set_timeout,
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};
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static struct watchdog_device wdt_dev = {
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.info = &wdt_info,
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.ops = &wdt_ops,
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.min_timeout = 1,
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.max_timeout = WDT_TIMEOUT_MAX,
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};
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static int wdt_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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unsigned char conf;
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int ret = -ENODEV;
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if (pci_enable_device(pdev)) {
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dev_err(&pdev->dev, "cannot enable PCI device\n");
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return -ENODEV;
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}
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/*
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* Allocate a MMIO region which contains watchdog control register
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* and counter, then configure the watchdog to use this region.
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* This is possible only if PnP is properly enabled in BIOS.
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* If not, the watchdog must be configured in BIOS manually.
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*/
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if (allocate_resource(&iomem_resource, &wdt_res, VIA_WDT_MMIO_LEN,
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0xf0000000, 0xffffff00, 0xff, NULL, NULL)) {
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dev_err(&pdev->dev, "MMIO allocation failed\n");
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goto err_out_disable_device;
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}
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pci_write_config_dword(pdev, VIA_WDT_MMIO_BASE, wdt_res.start);
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pci_read_config_byte(pdev, VIA_WDT_CONF, &conf);
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conf |= VIA_WDT_CONF_ENABLE | VIA_WDT_CONF_MMIO;
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pci_write_config_byte(pdev, VIA_WDT_CONF, conf);
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pci_read_config_dword(pdev, VIA_WDT_MMIO_BASE, &mmio);
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if (mmio) {
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dev_info(&pdev->dev, "VIA Chipset watchdog MMIO: %x\n", mmio);
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} else {
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dev_err(&pdev->dev, "MMIO setting failed. Check BIOS.\n");
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goto err_out_resource;
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}
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if (!request_mem_region(mmio, VIA_WDT_MMIO_LEN, "via_wdt")) {
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dev_err(&pdev->dev, "MMIO region busy\n");
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goto err_out_resource;
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}
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wdt_mem = ioremap(mmio, VIA_WDT_MMIO_LEN);
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if (wdt_mem == NULL) {
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dev_err(&pdev->dev, "cannot remap VIA wdt MMIO registers\n");
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goto err_out_release;
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}
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if (timeout < 1 || timeout > WDT_TIMEOUT_MAX)
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timeout = WDT_TIMEOUT;
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wdt_dev.timeout = timeout;
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wdt_dev.parent = &pdev->dev;
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watchdog_set_nowayout(&wdt_dev, nowayout);
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if (readl(wdt_mem) & VIA_WDT_FIRED)
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wdt_dev.bootstatus |= WDIOF_CARDRESET;
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ret = watchdog_register_device(&wdt_dev);
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if (ret)
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goto err_out_iounmap;
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/* start triggering, in case of watchdog already enabled by BIOS */
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mod_timer(&timer, jiffies + WDT_HEARTBEAT);
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return 0;
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err_out_iounmap:
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iounmap(wdt_mem);
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err_out_release:
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release_mem_region(mmio, VIA_WDT_MMIO_LEN);
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err_out_resource:
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release_resource(&wdt_res);
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err_out_disable_device:
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pci_disable_device(pdev);
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return ret;
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}
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static void wdt_remove(struct pci_dev *pdev)
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{
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watchdog_unregister_device(&wdt_dev);
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del_timer_sync(&timer);
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iounmap(wdt_mem);
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release_mem_region(mmio, VIA_WDT_MMIO_LEN);
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release_resource(&wdt_res);
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pci_disable_device(pdev);
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}
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static const struct pci_device_id wdt_pci_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700) },
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{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800) },
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{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855) },
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{ 0 }
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};
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static struct pci_driver wdt_driver = {
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.name = "via_wdt",
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.id_table = wdt_pci_table,
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.probe = wdt_probe,
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.remove = wdt_remove,
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};
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module_pci_driver(wdt_driver);
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MODULE_AUTHOR("Marc Vertes");
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MODULE_DESCRIPTION("Driver for watchdog timer on VIA chipset");
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MODULE_LICENSE("GPL");
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