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a809d46066
With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III mode through .set mips3 results in *lots* of warnings like {standard input}: Assembler messages: {standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension during a kernel build. Fixed by using .set arch=r4000 instead. This breaks support for building the kernel with binutils 2.13 which was supported for 32 bit kernels only anyway and 2.14 which was a bad vintage for MIPS anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
245 lines
5.4 KiB
C
245 lines
5.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2000, 2001, 05 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2001 MIPS Technologies, Inc.
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*/
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#include <linux/capability.h>
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/fs.h>
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#include <linux/smp.h>
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#include <linux/ptrace.h>
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#include <linux/string.h>
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#include <linux/syscalls.h>
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#include <linux/file.h>
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#include <linux/utsname.h>
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#include <linux/unistd.h>
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#include <linux/sem.h>
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#include <linux/msg.h>
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#include <linux/shm.h>
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#include <linux/compiler.h>
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#include <linux/ipc.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/elf.h>
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#include <asm/asm.h>
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#include <asm/branch.h>
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#include <asm/cachectl.h>
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#include <asm/cacheflush.h>
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#include <asm/asm-offsets.h>
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#include <asm/signal.h>
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#include <asm/sim.h>
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#include <asm/shmparam.h>
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#include <asm/sysmips.h>
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#include <asm/uaccess.h>
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#include <asm/switch_to.h>
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/*
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* For historic reasons the pipe(2) syscall on MIPS has an unusual calling
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* convention. It returns results in registers $v0 / $v1 which means there
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* is no need for it to do verify the validity of a userspace pointer
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* argument. Historically that used to be expensive in Linux. These days
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* the performance advantage is negligible.
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*/
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asmlinkage int sysm_pipe(void)
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{
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int fd[2];
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int error = do_pipe_flags(fd, 0);
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if (error)
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return error;
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current_pt_regs()->regs[3] = fd[1];
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return fd[0];
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}
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SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
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unsigned long, prot, unsigned long, flags, unsigned long,
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fd, off_t, offset)
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{
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unsigned long result;
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result = -EINVAL;
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if (offset & ~PAGE_MASK)
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goto out;
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result = sys_mmap_pgoff(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
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out:
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return result;
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}
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SYSCALL_DEFINE6(mips_mmap2, unsigned long, addr, unsigned long, len,
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unsigned long, prot, unsigned long, flags, unsigned long, fd,
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unsigned long, pgoff)
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{
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if (pgoff & (~PAGE_MASK >> 12))
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return -EINVAL;
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return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff >> (PAGE_SHIFT-12));
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}
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save_static_function(sys_fork);
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save_static_function(sys_clone);
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SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
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{
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struct thread_info *ti = task_thread_info(current);
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ti->tp_value = addr;
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if (cpu_has_userlocal)
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write_c0_userlocal(addr);
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return 0;
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}
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static inline int mips_atomic_set(unsigned long addr, unsigned long new)
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{
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unsigned long old, tmp;
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struct pt_regs *regs;
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unsigned int err;
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if (unlikely(addr & 3))
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return -EINVAL;
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if (unlikely(!access_ok(VERIFY_WRITE, addr, 4)))
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return -EINVAL;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__ (
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" .set arch=r4000 \n"
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" li %[err], 0 \n"
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"1: ll %[old], (%[addr]) \n"
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" move %[tmp], %[new] \n"
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"2: sc %[tmp], (%[addr]) \n"
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" beqzl %[tmp], 1b \n"
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"3: \n"
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" .section .fixup,\"ax\" \n"
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"4: li %[err], %[efault] \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 4b \n"
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" "STR(PTR)" 2b, 4b \n"
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" .previous \n"
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" .set mips0 \n"
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: [old] "=&r" (old),
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[err] "=&r" (err),
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[tmp] "=&r" (tmp)
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: [addr] "r" (addr),
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[new] "r" (new),
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[efault] "i" (-EFAULT)
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: "memory");
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} else if (cpu_has_llsc) {
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__asm__ __volatile__ (
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" .set arch=r4000 \n"
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" li %[err], 0 \n"
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"1: ll %[old], (%[addr]) \n"
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" move %[tmp], %[new] \n"
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"2: sc %[tmp], (%[addr]) \n"
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" bnez %[tmp], 4f \n"
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"3: \n"
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" .subsection 2 \n"
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"4: b 1b \n"
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" .previous \n"
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" \n"
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" .section .fixup,\"ax\" \n"
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"5: li %[err], %[efault] \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 5b \n"
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" "STR(PTR)" 2b, 5b \n"
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" .previous \n"
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" .set mips0 \n"
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: [old] "=&r" (old),
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[err] "=&r" (err),
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[tmp] "=&r" (tmp)
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: [addr] "r" (addr),
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[new] "r" (new),
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[efault] "i" (-EFAULT)
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: "memory");
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} else {
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do {
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preempt_disable();
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ll_bit = 1;
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ll_task = current;
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preempt_enable();
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err = __get_user(old, (unsigned int *) addr);
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err |= __put_user(new, (unsigned int *) addr);
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if (err)
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break;
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rmb();
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} while (!ll_bit);
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}
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if (unlikely(err))
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return err;
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regs = current_pt_regs();
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regs->regs[2] = old;
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regs->regs[7] = 0; /* No error */
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/*
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* Don't let your children do this ...
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*/
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__asm__ __volatile__(
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" move $29, %0 \n"
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" j syscall_exit \n"
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: /* no outputs */
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: "r" (regs));
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/* unreached. Honestly. */
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unreachable();
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}
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SYSCALL_DEFINE3(sysmips, long, cmd, long, arg1, long, arg2)
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{
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switch (cmd) {
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case MIPS_ATOMIC_SET:
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return mips_atomic_set(arg1, arg2);
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case MIPS_FIXADE:
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if (arg1 & ~3)
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return -EINVAL;
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if (arg1 & 1)
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set_thread_flag(TIF_FIXADE);
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else
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clear_thread_flag(TIF_FIXADE);
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if (arg1 & 2)
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set_thread_flag(TIF_LOGADE);
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else
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clear_thread_flag(TIF_LOGADE);
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return 0;
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case FLUSH_CACHE:
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__flush_cache_all();
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return 0;
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}
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return -EINVAL;
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}
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/*
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* No implemented yet ...
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*/
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SYSCALL_DEFINE3(cachectl, char *, addr, int, nbytes, int, op)
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{
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return -ENOSYS;
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}
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/*
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* If we ever come here the user sp is bad. Zap the process right away.
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* Due to the bad stack signaling wouldn't work.
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*/
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asmlinkage void bad_stack(void)
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{
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do_exit(SIGSEGV);
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}
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