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entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJS4WZPAAoJEDqPOy9afJhJVz4QAL63xispjEVuABUjgskR1fyo 7QljpqUJCOViqiVqNi1sPtM0irvfrApNwTpK3mGm20/kbNIBSdqGc/fI5CbWxXAU scRqplTTLY6F7nXJXGgiM/e5b31Tb+KmY9Su5chq1Yv6py4/yb6SzoohcBlQJ5in JKIxgLqe1VqUkCY2EFlqLwYqUtgr/Zm6ZJDt4LTwxc43apwgG7USMAS8ppx7nTgd oGgcsU4dNur1L4+ahvwqC+ntfoZNmVKJm+eY+JrHXJ2sga4PLaJcorgK2NXFpgln nwZQzRfbZLg7vNg/ODIDvP94mhc266xq2TCWzD/kMOBwmhsM0lySpzI/IM8qv1U2 Tdy9EHAj2iHoU+s1yPEUtNRV4h2+BGUUy54690XO30+VCLVEJUCC2KopDAk0G3ua qxSCb1mJto8EEq3jCJwKZSOUI7gcizDjHAaqfLlnDytMlsFJR7AJVj5IcRdgC/9s Vg975Xklkn33fWEuYQzdQdcmJ8ZCnydo92R2S0CaMgxMZqp2eoYZXJWvgCAvfQYC HjAtnBpHxNsZQeASvclb9bQrEisAUjIrxvuzLenQhg88WhBuyUDgBdretCzHFhP4 i62QGAhSYiNJJQzs+U9EndG6fRr/p98Pmw2pBAAn8UYOT2wWMj8wpR+IVT50Bmdi j6LsDpvc7CE2a4f+KoCa =Hh66 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
193 lines
3.3 KiB
Plaintext
193 lines
3.3 KiB
Plaintext
* Samsung Exynos5250 Clock Controller
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The Exynos5250 clock controller generates and supplies clock to various
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controllers within the Exynos5250 SoC.
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Required Properties:
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- compatible: should be one of the following.
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- "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume.
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[Core Clocks]
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Clock ID
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----------------------------
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fin_pll 1
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[Clock Gate for Special Clocks]
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Clock ID
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----------------------------
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sclk_cam_bayer 128
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sclk_cam0 129
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sclk_cam1 130
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sclk_gscl_wa 131
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sclk_gscl_wb 132
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sclk_fimd1 133
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sclk_mipi1 134
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sclk_dp 135
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sclk_hdmi 136
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sclk_pixel 137
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sclk_audio0 138
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sclk_mmc0 139
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sclk_mmc1 140
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sclk_mmc2 141
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sclk_mmc3 142
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sclk_sata 143
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sclk_usb3 144
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sclk_jpeg 145
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sclk_uart0 146
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sclk_uart1 147
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sclk_uart2 148
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sclk_uart3 149
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sclk_pwm 150
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sclk_audio1 151
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sclk_audio2 152
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sclk_spdif 153
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sclk_spi0 154
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sclk_spi1 155
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sclk_spi2 156
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div_i2s1 157
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div_i2s2 158
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sclk_hdmiphy 159
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div_pcm0 160
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[Peripheral Clock Gates]
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Clock ID
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----------------------------
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gscl0 256
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gscl1 257
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gscl2 258
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gscl3 259
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gscl_wa 260
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gscl_wb 261
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smmu_gscl0 262
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smmu_gscl1 263
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smmu_gscl2 264
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smmu_gscl3 265
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mfc 266
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smmu_mfcl 267
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smmu_mfcr 268
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rotator 269
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jpeg 270
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mdma1 271
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smmu_rotator 272
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smmu_jpeg 273
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smmu_mdma1 274
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pdma0 275
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pdma1 276
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sata 277
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usbotg 278
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mipi_hsi 279
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sdmmc0 280
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sdmmc1 281
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sdmmc2 282
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sdmmc3 283
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sromc 284
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usb2 285
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usb3 286
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sata_phyctrl 287
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sata_phyi2c 288
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uart0 289
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uart1 290
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uart2 291
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uart3 292
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uart4 293
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i2c0 294
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i2c1 295
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i2c2 296
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i2c3 297
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i2c4 298
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i2c5 299
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i2c6 300
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i2c7 301
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i2c_hdmi 302
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adc 303
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spi0 304
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spi1 305
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spi2 306
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i2s1 307
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i2s2 308
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pcm1 309
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pcm2 310
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pwm 311
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spdif 312
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ac97 313
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hsi2c0 314
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hsi2c1 315
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hs12c2 316
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hs12c3 317
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chipid 318
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sysreg 319
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pmu 320
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cmu_top 321
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cmu_core 322
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cmu_mem 323
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tzpc0 324
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tzpc1 325
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tzpc2 326
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tzpc3 327
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tzpc4 328
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tzpc5 329
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tzpc6 330
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tzpc7 331
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tzpc8 332
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tzpc9 333
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hdmi_cec 334
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mct 335
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wdt 336
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rtc 337
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tmu 338
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fimd1 339
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mie1 340
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dsim0 341
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dp 342
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mixer 343
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hdmi 344
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g2d 345
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mdma0 346
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smmu_mdma0 347
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[Clock Muxes]
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Clock ID
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----------------------------
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mout_hdmi 1024
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Example 1: An example of a clock controller node is listed below.
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clock: clock-controller@0x10010000 {
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compatible = "samsung,exynos5250-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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Example 2: UART controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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serial@13820000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13820000 0x100>;
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interrupts = <0 54 0>;
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clocks = <&clock 314>, <&clock 153>;
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clock-names = "uart", "clk_uart_baud0";
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};
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