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042000b003
Adds the main PLL clock groups for SOCFPGA into device tree file so that the clock framework to query the clock and clock rates appropriately. $cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc1 2 2 25000000 sdram_pll 0 0 400000000 s2f_usr2_clk 0 0 66666666 ddr_dq_clk 0 0 200000000 ddr_2x_dqs_clk 0 0 400000000 ddr_dqs_clk 0 0 200000000 periph_pll 2 2 500000000 s2f_usr1_clk 0 0 50000000 per_base_clk 4 4 100000000 per_nand_mmc_clk 0 0 25000000 per_qsi_clk 0 0 250000000 emac1_clk 1 1 125000000 emac0_clk 0 0 125000000 main_pll 1 1 1600000000 cfg_s2f_usr0_clk 0 0 100000000 main_nand_sdmmc_clk 0 0 100000000 main_qspi_clk 0 0 400000000 dbg_base_clk 0 0 400000000 mainclk 0 0 400000000 mpuclk 1 1 800000000 smp_twd 1 1 200000000 Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Signed-off-by: Olof Johansson <olof@lixom.net> |
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.. | ||
altr_socfpga.txt | ||
calxeda.txt | ||
clock-bindings.txt | ||
fixed-clock.txt | ||
imx5-clock.txt | ||
imx6q-clock.txt | ||
imx23-clock.txt | ||
imx25-clock.txt | ||
imx28-clock.txt | ||
imx31-clock.txt | ||
mvebu-core-clock.txt | ||
mvebu-cpu-clock.txt | ||
mvebu-gated-clock.txt | ||
nvidia,tegra20-car.txt | ||
nvidia,tegra30-car.txt | ||
prima2-clock.txt | ||
vt8500.txt | ||
zynq-7000.txt |