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384461abca
Instead of requiring each driver to care for assigning the owner member
of struct pwm_ops, handle that implicitly using a macro. Note that the
owner member has to be moved to struct pwm_chip, as the ops structure
usually lives in read-only memory and so cannot be modified.
The upside is that new low level drivers cannot forget the assignment and
save one line each. The pwm-crc driver didn't assign .owner, that's not
a problem in practice though as the driver cannot be compiled as a
module.
Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> # Intel LPSS
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> # pwm-{bcm,brcm}*.c
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> # sun4i
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Acked-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> # pwm-visconti
Acked-by: Heiko Stuebner <heiko@sntech.de> # pwm-rockchip
Acked-by: Michael Walle <michael@walle.cc> # pwm-sl28cpld
Acked-by: Neil Armstrong <neil.armstrong@linaro.org> # pwm-meson
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230804142707.412137-2-u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
401 lines
9.3 KiB
C
401 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PWM driver for Rockchip SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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* Copyright (C) 2014 ROCKCHIP, Inc.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/time.h>
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#define PWM_CTRL_TIMER_EN (1 << 0)
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#define PWM_CTRL_OUTPUT_EN (1 << 3)
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#define PWM_ENABLE (1 << 0)
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#define PWM_CONTINUOUS (1 << 1)
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#define PWM_DUTY_POSITIVE (1 << 3)
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#define PWM_DUTY_NEGATIVE (0 << 3)
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#define PWM_INACTIVE_NEGATIVE (0 << 4)
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#define PWM_INACTIVE_POSITIVE (1 << 4)
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#define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
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#define PWM_OUTPUT_LEFT (0 << 5)
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#define PWM_LOCK_EN (1 << 6)
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#define PWM_LP_DISABLE (0 << 8)
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struct rockchip_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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struct clk *pclk;
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const struct rockchip_pwm_data *data;
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void __iomem *base;
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};
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struct rockchip_pwm_regs {
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unsigned long duty;
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unsigned long period;
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unsigned long cntr;
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unsigned long ctrl;
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};
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struct rockchip_pwm_data {
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struct rockchip_pwm_regs regs;
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unsigned int prescaler;
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bool supports_polarity;
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bool supports_lock;
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u32 enable_conf;
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};
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static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct rockchip_pwm_chip, chip);
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}
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static int rockchip_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 enable_conf = pc->data->enable_conf;
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unsigned long clk_rate;
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u64 tmp;
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u32 val;
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int ret;
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ret = clk_enable(pc->pclk);
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if (ret)
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return ret;
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(pc->clk);
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tmp = readl_relaxed(pc->base + pc->data->regs.period);
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tmp *= pc->data->prescaler * NSEC_PER_SEC;
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
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tmp = readl_relaxed(pc->base + pc->data->regs.duty);
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tmp *= pc->data->prescaler * NSEC_PER_SEC;
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
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val = readl_relaxed(pc->base + pc->data->regs.ctrl);
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state->enabled = (val & enable_conf) == enable_conf;
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if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
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state->polarity = PWM_POLARITY_INVERSED;
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else
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state->polarity = PWM_POLARITY_NORMAL;
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clk_disable(pc->clk);
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clk_disable(pc->pclk);
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return 0;
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}
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static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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unsigned long period, duty;
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u64 clk_rate, div;
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u32 ctrl;
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clk_rate = clk_get_rate(pc->clk);
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/*
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* Since period and duty cycle registers have a width of 32
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* bits, every possible input period can be obtained using the
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* default prescaler value for all practical clock rate values.
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*/
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div = clk_rate * state->period;
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period = DIV_ROUND_CLOSEST_ULL(div,
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pc->data->prescaler * NSEC_PER_SEC);
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div = clk_rate * state->duty_cycle;
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duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
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/*
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* Lock the period and duty of previous configuration, then
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* change the duty and period, that would not be effective.
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*/
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ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
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if (pc->data->supports_lock) {
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ctrl |= PWM_LOCK_EN;
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writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
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}
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writel(period, pc->base + pc->data->regs.period);
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writel(duty, pc->base + pc->data->regs.duty);
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if (pc->data->supports_polarity) {
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ctrl &= ~PWM_POLARITY_MASK;
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if (state->polarity == PWM_POLARITY_INVERSED)
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ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
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else
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ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
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}
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/*
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* Unlock and set polarity at the same time,
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* the configuration of duty, period and polarity
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* would be effective together at next period.
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*/
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if (pc->data->supports_lock)
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ctrl &= ~PWM_LOCK_EN;
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writel(ctrl, pc->base + pc->data->regs.ctrl);
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}
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static int rockchip_pwm_enable(struct pwm_chip *chip,
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struct pwm_device *pwm,
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bool enable)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 enable_conf = pc->data->enable_conf;
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int ret;
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u32 val;
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if (enable) {
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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}
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val = readl_relaxed(pc->base + pc->data->regs.ctrl);
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if (enable)
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val |= enable_conf;
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else
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val &= ~enable_conf;
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writel_relaxed(val, pc->base + pc->data->regs.ctrl);
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if (!enable)
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clk_disable(pc->clk);
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return 0;
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}
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static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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struct pwm_state curstate;
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bool enabled;
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int ret = 0;
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ret = clk_enable(pc->pclk);
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if (ret)
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return ret;
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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pwm_get_state(pwm, &curstate);
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enabled = curstate.enabled;
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if (state->polarity != curstate.polarity && enabled &&
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!pc->data->supports_lock) {
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ret = rockchip_pwm_enable(chip, pwm, false);
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if (ret)
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goto out;
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enabled = false;
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}
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rockchip_pwm_config(chip, pwm, state);
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if (state->enabled != enabled) {
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ret = rockchip_pwm_enable(chip, pwm, state->enabled);
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if (ret)
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goto out;
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}
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out:
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clk_disable(pc->clk);
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clk_disable(pc->pclk);
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return ret;
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}
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static const struct pwm_ops rockchip_pwm_ops = {
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.get_state = rockchip_pwm_get_state,
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.apply = rockchip_pwm_apply,
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};
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static const struct rockchip_pwm_data pwm_data_v1 = {
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.regs = {
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.duty = 0x04,
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.period = 0x08,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 2,
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.supports_polarity = false,
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.supports_lock = false,
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.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
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};
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static const struct rockchip_pwm_data pwm_data_v2 = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = false,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
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PWM_CONTINUOUS,
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};
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static const struct rockchip_pwm_data pwm_data_vop = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x0c,
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.ctrl = 0x00,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = false,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
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PWM_CONTINUOUS,
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};
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static const struct rockchip_pwm_data pwm_data_v3 = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = true,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
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PWM_CONTINUOUS,
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};
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static const struct of_device_id rockchip_pwm_dt_ids[] = {
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{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
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{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
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{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
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{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
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static int rockchip_pwm_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct rockchip_pwm_chip *pc;
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u32 enable_conf, ctrl;
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bool enabled;
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int ret, count;
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id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
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if (!id)
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return -EINVAL;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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pc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pc->base))
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return PTR_ERR(pc->base);
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pc->clk = devm_clk_get(&pdev->dev, "pwm");
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if (IS_ERR(pc->clk)) {
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pc->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pc->clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
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"Can't get PWM clk\n");
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}
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count = of_count_phandle_with_args(pdev->dev.of_node,
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"clocks", "#clock-cells");
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if (count == 2)
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pc->pclk = devm_clk_get(&pdev->dev, "pclk");
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else
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pc->pclk = pc->clk;
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if (IS_ERR(pc->pclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n");
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ret = clk_prepare_enable(pc->clk);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "Can't prepare enable PWM clk\n");
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ret = clk_prepare_enable(pc->pclk);
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if (ret) {
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dev_err_probe(&pdev->dev, ret, "Can't prepare enable APB clk\n");
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goto err_clk;
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}
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platform_set_drvdata(pdev, pc);
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pc->data = id->data;
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &rockchip_pwm_ops;
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pc->chip.npwm = 1;
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enable_conf = pc->data->enable_conf;
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ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
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enabled = (ctrl & enable_conf) == enable_conf;
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
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goto err_pclk;
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}
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/* Keep the PWM clk enabled if the PWM appears to be up and running. */
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if (!enabled)
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clk_disable(pc->clk);
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clk_disable(pc->pclk);
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return 0;
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err_pclk:
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clk_disable_unprepare(pc->pclk);
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err_clk:
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clk_disable_unprepare(pc->clk);
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return ret;
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}
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static void rockchip_pwm_remove(struct platform_device *pdev)
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{
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struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
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pwmchip_remove(&pc->chip);
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clk_unprepare(pc->pclk);
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clk_unprepare(pc->clk);
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}
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static struct platform_driver rockchip_pwm_driver = {
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.driver = {
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.name = "rockchip-pwm",
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.of_match_table = rockchip_pwm_dt_ids,
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},
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.probe = rockchip_pwm_probe,
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.remove_new = rockchip_pwm_remove,
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};
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module_platform_driver(rockchip_pwm_driver);
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MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
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MODULE_DESCRIPTION("Rockchip SoC PWM driver");
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MODULE_LICENSE("GPL v2");
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