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035e111f9a
The two chips are somewhat different, and needs different handling. Adds handing of the dma, dram initialization, hardware settings, io, memory arbiter and pinmux Also moves the dma, dram initialization and io from CRIS v32 common files.
310 lines
7.6 KiB
C
310 lines
7.6 KiB
C
/*
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* Allocator for I/O pins. All pins are allocated to GPIO at bootup.
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* Unassigned pins and GPIO pins can be allocated to a fixed interface
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* or the I/O processor instead.
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*
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* Copyright (c) 2004-2007 Axis Communications AB.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/spinlock.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <pinmux.h>
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#include <hwregs/pinmux_defs.h>
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#undef DEBUG
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#define PORT_PINS 18
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#define PORTS 4
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static char pins[PORTS][PORT_PINS];
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static DEFINE_SPINLOCK(pinmux_lock);
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static void crisv32_pinmux_set(int port);
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int crisv32_pinmux_init(void)
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{
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static int initialized;
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if (!initialized) {
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reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa);
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initialized = 1;
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REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
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pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 =
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pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes;
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REG_WR(pinmux, regi_pinmux, rw_pa, pa);
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crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio);
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crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio);
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crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio);
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crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio);
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}
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return 0;
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}
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int
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crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
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{
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int i;
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unsigned long flags;
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crisv32_pinmux_init();
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if (port > PORTS)
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return -EINVAL;
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spin_lock_irqsave(&pinmux_lock, flags);
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for (i = first_pin; i <= last_pin; i++) {
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if ((pins[port][i] != pinmux_none)
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&& (pins[port][i] != pinmux_gpio)
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&& (pins[port][i] != mode)) {
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spin_unlock_irqrestore(&pinmux_lock, flags);
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#ifdef DEBUG
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panic("Pinmux alloc failed!\n");
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#endif
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return -EPERM;
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}
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}
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for (i = first_pin; i <= last_pin; i++)
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pins[port][i] = mode;
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crisv32_pinmux_set(port);
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return 0;
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}
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int crisv32_pinmux_alloc_fixed(enum fixed_function function)
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{
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int ret = -EINVAL;
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char saved[sizeof pins];
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unsigned long flags;
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spin_lock_irqsave(&pinmux_lock, flags);
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/* Save internal data for recovery */
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memcpy(saved, pins, sizeof pins);
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crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */
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reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
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switch (function) {
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case pinmux_ser1:
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ret = crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed);
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hwprot.ser1 = regk_pinmux_yes;
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break;
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case pinmux_ser2:
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ret = crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed);
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hwprot.ser2 = regk_pinmux_yes;
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break;
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case pinmux_ser3:
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ret = crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed);
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hwprot.ser3 = regk_pinmux_yes;
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break;
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case pinmux_sser0:
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ret = crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
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hwprot.sser0 = regk_pinmux_yes;
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break;
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case pinmux_sser1:
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ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
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hwprot.sser1 = regk_pinmux_yes;
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break;
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case pinmux_ata0:
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ret = crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed);
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hwprot.ata0 = regk_pinmux_yes;
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break;
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case pinmux_ata1:
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ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed);
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hwprot.ata1 = regk_pinmux_yes;
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break;
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case pinmux_ata2:
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ret = crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed);
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hwprot.ata2 = regk_pinmux_yes;
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break;
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case pinmux_ata3:
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ret = crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed);
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hwprot.ata2 = regk_pinmux_yes;
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break;
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case pinmux_ata:
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ret = crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed);
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ret |= crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed);
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hwprot.ata = regk_pinmux_yes;
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break;
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case pinmux_eth1:
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ret = crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed);
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hwprot.eth1 = regk_pinmux_yes;
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hwprot.eth1_mgm = regk_pinmux_yes;
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break;
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case pinmux_timer:
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ret = crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
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hwprot.timer = regk_pinmux_yes;
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return ret;
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}
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if (!ret)
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REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
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else
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memcpy(pins, saved, sizeof pins);
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return ret;
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}
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void crisv32_pinmux_set(int port)
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{
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int i;
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int gpio_val = 0;
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int iop_val = 0;
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for (i = 0; i < PORT_PINS; i++) {
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if (pins[port][i] == pinmux_gpio)
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gpio_val |= (1 << i);
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else if (pins[port][i] == pinmux_iop)
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iop_val |= (1 << i);
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}
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REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8 * port,
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gpio_val);
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REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8 * port,
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iop_val);
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#ifdef DEBUG
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crisv32_pinmux_dump();
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#endif
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}
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int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
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{
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int i;
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unsigned long flags;
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crisv32_pinmux_init();
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if (port > PORTS)
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return -EINVAL;
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spin_lock_irqsave(&pinmux_lock, flags);
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for (i = first_pin; i <= last_pin; i++)
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pins[port][i] = pinmux_none;
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crisv32_pinmux_set(port);
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return 0;
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}
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int crisv32_pinmux_dealloc_fixed(enum fixed_function function)
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{
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int ret = -EINVAL;
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char saved[sizeof pins];
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unsigned long flags;
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spin_lock_irqsave(&pinmux_lock, flags);
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/* Save internal data for recovery */
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memcpy(saved, pins, sizeof pins);
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crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */
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reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
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switch (function) {
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case pinmux_ser1:
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ret = crisv32_pinmux_dealloc(PORT_C, 4, 7);
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hwprot.ser1 = regk_pinmux_no;
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break;
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case pinmux_ser2:
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ret = crisv32_pinmux_dealloc(PORT_C, 8, 11);
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hwprot.ser2 = regk_pinmux_no;
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break;
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case pinmux_ser3:
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ret = crisv32_pinmux_dealloc(PORT_C, 12, 15);
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hwprot.ser3 = regk_pinmux_no;
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break;
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case pinmux_sser0:
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ret = crisv32_pinmux_dealloc(PORT_C, 0, 3);
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ret |= crisv32_pinmux_dealloc(PORT_C, 16, 16);
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hwprot.sser0 = regk_pinmux_no;
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break;
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case pinmux_sser1:
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ret = crisv32_pinmux_dealloc(PORT_D, 0, 4);
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hwprot.sser1 = regk_pinmux_no;
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break;
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case pinmux_ata0:
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ret = crisv32_pinmux_dealloc(PORT_D, 5, 7);
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ret |= crisv32_pinmux_dealloc(PORT_D, 15, 17);
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hwprot.ata0 = regk_pinmux_no;
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break;
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case pinmux_ata1:
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ret = crisv32_pinmux_dealloc(PORT_D, 0, 4);
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ret |= crisv32_pinmux_dealloc(PORT_E, 17, 17);
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hwprot.ata1 = regk_pinmux_no;
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break;
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case pinmux_ata2:
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ret = crisv32_pinmux_dealloc(PORT_C, 11, 15);
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ret |= crisv32_pinmux_dealloc(PORT_E, 3, 3);
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hwprot.ata2 = regk_pinmux_no;
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break;
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case pinmux_ata3:
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ret = crisv32_pinmux_dealloc(PORT_C, 8, 10);
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ret |= crisv32_pinmux_dealloc(PORT_C, 0, 2);
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hwprot.ata2 = regk_pinmux_no;
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break;
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case pinmux_ata:
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ret = crisv32_pinmux_dealloc(PORT_B, 0, 15);
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ret |= crisv32_pinmux_dealloc(PORT_D, 8, 15);
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hwprot.ata = regk_pinmux_no;
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break;
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case pinmux_eth1:
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ret = crisv32_pinmux_dealloc(PORT_E, 0, 17);
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hwprot.eth1 = regk_pinmux_no;
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hwprot.eth1_mgm = regk_pinmux_no;
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break;
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case pinmux_timer:
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ret = crisv32_pinmux_dealloc(PORT_C, 16, 16);
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hwprot.timer = regk_pinmux_no;
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return ret;
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}
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if (!ret)
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REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
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else
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memcpy(pins, saved, sizeof pins);
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spin_unlock_irqrestore(&pinmux_lock, flags);
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return ret;
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}
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void crisv32_pinmux_dump(void)
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{
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int i, j;
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crisv32_pinmux_init();
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for (i = 0; i < PORTS; i++) {
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printk(KERN_DEBUG "Port %c\n", 'B' + i);
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for (j = 0; j < PORT_PINS; j++)
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printk(KERN_DEBUG " Pin %d = %d\n", j, pins[i][j]);
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}
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}
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__initcall(crisv32_pinmux_init);
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