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3e5ee32392
Old gcc versions may fail with an internal compiler error if only the
T or S constraint is specified for an operand, and no displacement is
needed at all.
To fix this use RT and QS as constraints, which reflects the union of
both. Later gcc versions do the right thing and always accept single T
and S constraints.
See gcc commit 3e4be43f69da ("S/390: Memory constraint cleanup").
Fixes: ca897bb181 ("s390/atomic: use proper constraints")
Fixes: b23eb636d7 ("s390/atomic: get rid of gcc atomic builtins")
Fixes: d2b1f6d2d3 ("s390/cmpxchg: get rid of gcc atomic builtins")
Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
202 lines
5.0 KiB
C
202 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Low level function for atomic operations
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*
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* Copyright IBM Corp. 1999, 2016
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*/
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#ifndef __ARCH_S390_ATOMIC_OPS__
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#define __ARCH_S390_ATOMIC_OPS__
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static inline int __atomic_read(const atomic_t *v)
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{
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int c;
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asm volatile(
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" l %0,%1\n"
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: "=d" (c) : "R" (v->counter));
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return c;
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}
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static inline void __atomic_set(atomic_t *v, int i)
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{
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asm volatile(
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" st %1,%0\n"
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: "=R" (v->counter) : "d" (i));
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}
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static inline s64 __atomic64_read(const atomic64_t *v)
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{
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s64 c;
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asm volatile(
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" lg %0,%1\n"
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: "=d" (c) : "RT" (v->counter));
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return c;
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}
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static inline void __atomic64_set(atomic64_t *v, s64 i)
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{
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asm volatile(
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" stg %1,%0\n"
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: "=RT" (v->counter) : "d" (i));
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}
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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#define __ATOMIC_OP(op_name, op_type, op_string, op_barrier) \
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static inline op_type op_name(op_type val, op_type *ptr) \
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{ \
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op_type old; \
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\
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asm volatile( \
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op_string " %[old],%[val],%[ptr]\n" \
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op_barrier \
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: [old] "=d" (old), [ptr] "+QS" (*ptr) \
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: [val] "d" (val) : "cc", "memory"); \
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return old; \
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} \
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#define __ATOMIC_OPS(op_name, op_type, op_string) \
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__ATOMIC_OP(op_name, op_type, op_string, "\n") \
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__ATOMIC_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")
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__ATOMIC_OPS(__atomic_add, int, "laa")
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__ATOMIC_OPS(__atomic_and, int, "lan")
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__ATOMIC_OPS(__atomic_or, int, "lao")
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__ATOMIC_OPS(__atomic_xor, int, "lax")
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__ATOMIC_OPS(__atomic64_add, long, "laag")
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__ATOMIC_OPS(__atomic64_and, long, "lang")
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__ATOMIC_OPS(__atomic64_or, long, "laog")
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__ATOMIC_OPS(__atomic64_xor, long, "laxg")
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#undef __ATOMIC_OPS
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#undef __ATOMIC_OP
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#define __ATOMIC_CONST_OP(op_name, op_type, op_string, op_barrier) \
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static __always_inline void op_name(op_type val, op_type *ptr) \
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{ \
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asm volatile( \
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op_string " %[ptr],%[val]\n" \
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op_barrier \
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: [ptr] "+QS" (*ptr) : [val] "i" (val) : "cc", "memory");\
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}
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#define __ATOMIC_CONST_OPS(op_name, op_type, op_string) \
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__ATOMIC_CONST_OP(op_name, op_type, op_string, "\n") \
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__ATOMIC_CONST_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")
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__ATOMIC_CONST_OPS(__atomic_add_const, int, "asi")
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__ATOMIC_CONST_OPS(__atomic64_add_const, long, "agsi")
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#undef __ATOMIC_CONST_OPS
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#undef __ATOMIC_CONST_OP
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#else /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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#define __ATOMIC_OP(op_name, op_string) \
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static inline int op_name(int val, int *ptr) \
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{ \
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int old, new; \
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\
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asm volatile( \
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"0: lr %[new],%[old]\n" \
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op_string " %[new],%[val]\n" \
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" cs %[old],%[new],%[ptr]\n" \
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" jl 0b" \
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: [old] "=d" (old), [new] "=&d" (new), [ptr] "+Q" (*ptr)\
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: [val] "d" (val), "0" (*ptr) : "cc", "memory"); \
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return old; \
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}
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#define __ATOMIC_OPS(op_name, op_string) \
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__ATOMIC_OP(op_name, op_string) \
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__ATOMIC_OP(op_name##_barrier, op_string)
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__ATOMIC_OPS(__atomic_add, "ar")
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__ATOMIC_OPS(__atomic_and, "nr")
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__ATOMIC_OPS(__atomic_or, "or")
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__ATOMIC_OPS(__atomic_xor, "xr")
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#undef __ATOMIC_OPS
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#define __ATOMIC64_OP(op_name, op_string) \
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static inline long op_name(long val, long *ptr) \
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{ \
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long old, new; \
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\
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asm volatile( \
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"0: lgr %[new],%[old]\n" \
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op_string " %[new],%[val]\n" \
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" csg %[old],%[new],%[ptr]\n" \
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" jl 0b" \
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: [old] "=d" (old), [new] "=&d" (new), [ptr] "+QS" (*ptr)\
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: [val] "d" (val), "0" (*ptr) : "cc", "memory"); \
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return old; \
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}
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#define __ATOMIC64_OPS(op_name, op_string) \
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__ATOMIC64_OP(op_name, op_string) \
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__ATOMIC64_OP(op_name##_barrier, op_string)
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__ATOMIC64_OPS(__atomic64_add, "agr")
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__ATOMIC64_OPS(__atomic64_and, "ngr")
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__ATOMIC64_OPS(__atomic64_or, "ogr")
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__ATOMIC64_OPS(__atomic64_xor, "xgr")
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#undef __ATOMIC64_OPS
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#define __atomic_add_const(val, ptr) __atomic_add(val, ptr)
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#define __atomic_add_const_barrier(val, ptr) __atomic_add(val, ptr)
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#define __atomic64_add_const(val, ptr) __atomic64_add(val, ptr)
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#define __atomic64_add_const_barrier(val, ptr) __atomic64_add(val, ptr)
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#endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */
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static inline int __atomic_cmpxchg(int *ptr, int old, int new)
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{
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asm volatile(
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" cs %[old],%[new],%[ptr]"
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: [old] "+d" (old), [ptr] "+Q" (*ptr)
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: [new] "d" (new)
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: "cc", "memory");
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return old;
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}
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static inline bool __atomic_cmpxchg_bool(int *ptr, int old, int new)
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{
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int old_expected = old;
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asm volatile(
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" cs %[old],%[new],%[ptr]"
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: [old] "+d" (old), [ptr] "+Q" (*ptr)
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: [new] "d" (new)
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: "cc", "memory");
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return old == old_expected;
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}
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static inline long __atomic64_cmpxchg(long *ptr, long old, long new)
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{
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asm volatile(
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" csg %[old],%[new],%[ptr]"
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: [old] "+d" (old), [ptr] "+QS" (*ptr)
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: [new] "d" (new)
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: "cc", "memory");
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return old;
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}
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static inline bool __atomic64_cmpxchg_bool(long *ptr, long old, long new)
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{
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long old_expected = old;
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asm volatile(
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" csg %[old],%[new],%[ptr]"
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: [old] "+d" (old), [ptr] "+QS" (*ptr)
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: [new] "d" (new)
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: "cc", "memory");
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return old == old_expected;
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}
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#endif /* __ARCH_S390_ATOMIC_OPS__ */
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