mirror of
https://github.com/torvalds/linux.git
synced 2024-11-07 20:51:47 +00:00
4f04d8f005
The virtual memory layout is described in Documentation/arm64/memory.txt. This patch adds the MMU definitions for the 4KB and 64KB translation table configurations. The SECTION_SIZE is 2MB with 4KB page and 512MB with 64KB page configuration. PHYS_OFFSET is calculated at run-time and stored in a variable (no run-time code patching at this stage). On the current implementation, both user and kernel address spaces are 512G (39-bit) each with a maximum of 256G for the RAM linear mapping. Linux uses 3 levels of translation tables with the 4K page configuration and 2 levels with the 64K configuration. Extending the memory space beyond 39-bit with the 4K pages or 42-bit with 64K pages requires an additional level of translation tables. The SPARSEMEM configuration is global to all AArch64 platforms and allows for 1GB sections with SPARSEMEM_VMEMMAP enabled by default. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
74 lines
3.1 KiB
Plaintext
74 lines
3.1 KiB
Plaintext
Memory Layout on AArch64 Linux
|
|
==============================
|
|
|
|
Author: Catalin Marinas <catalin.marinas@arm.com>
|
|
Date : 20 February 2012
|
|
|
|
This document describes the virtual memory layout used by the AArch64
|
|
Linux kernel. The architecture allows up to 4 levels of translation
|
|
tables with a 4KB page size and up to 3 levels with a 64KB page size.
|
|
|
|
AArch64 Linux uses 3 levels of translation tables with the 4KB page
|
|
configuration, allowing 39-bit (512GB) virtual addresses for both user
|
|
and kernel. With 64KB pages, only 2 levels of translation tables are
|
|
used but the memory layout is the same.
|
|
|
|
User addresses have bits 63:39 set to 0 while the kernel addresses have
|
|
the same bits set to 1. TTBRx selection is given by bit 63 of the
|
|
virtual address. The swapper_pg_dir contains only kernel (global)
|
|
mappings while the user pgd contains only user (non-global) mappings.
|
|
The swapper_pgd_dir address is written to TTBR1 and never written to
|
|
TTBR0.
|
|
|
|
|
|
AArch64 Linux memory layout:
|
|
|
|
Start End Size Use
|
|
-----------------------------------------------------------------------
|
|
0000000000000000 0000007fffffffff 512GB user
|
|
|
|
ffffff8000000000 ffffffbbfffcffff ~240GB vmalloc
|
|
|
|
ffffffbbfffd0000 ffffffbcfffdffff 64KB [guard page]
|
|
|
|
ffffffbbfffe0000 ffffffbcfffeffff 64KB PCI I/O space
|
|
|
|
ffffffbbffff0000 ffffffbcffffffff 64KB [guard page]
|
|
|
|
ffffffbc00000000 ffffffbdffffffff 8GB vmemmap
|
|
|
|
ffffffbe00000000 ffffffbffbffffff ~8GB [guard, future vmmemap]
|
|
|
|
ffffffbffc000000 ffffffbfffffffff 64MB modules
|
|
|
|
ffffffc000000000 ffffffffffffffff 256GB memory
|
|
|
|
|
|
Translation table lookup with 4KB pages:
|
|
|
|
+--------+--------+--------+--------+--------+--------+--------+--------+
|
|
|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
|
|
+--------+--------+--------+--------+--------+--------+--------+--------+
|
|
| | | | | |
|
|
| | | | | v
|
|
| | | | | [11:0] in-page offset
|
|
| | | | +-> [20:12] L3 index
|
|
| | | +-----------> [29:21] L2 index
|
|
| | +---------------------> [38:30] L1 index
|
|
| +-------------------------------> [47:39] L0 index (not used)
|
|
+-------------------------------------------------> [63] TTBR0/1
|
|
|
|
|
|
Translation table lookup with 64KB pages:
|
|
|
|
+--------+--------+--------+--------+--------+--------+--------+--------+
|
|
|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
|
|
+--------+--------+--------+--------+--------+--------+--------+--------+
|
|
| | | | |
|
|
| | | | v
|
|
| | | | [15:0] in-page offset
|
|
| | | +----------> [28:16] L3 index
|
|
| | +--------------------------> [41:29] L2 index (only 38:29 used)
|
|
| +-------------------------------> [47:42] L1 index (not used)
|
|
+-------------------------------------------------> [63] TTBR0/1
|