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4b92d4add5
DEFINE_SMP_CALL_CACHE_FUNCTION() was usefel before the CPU hotplug rework
to ensure that the cache related functions are called on the upcoming CPU
because the notifier itself could run on any online CPU.
The hotplug state machine guarantees that the callbacks are invoked on the
upcoming CPU. So there is no need to have this SMP function call
obfuscation. That indirection was missed when the hotplug notifiers were
converted.
This also solves the problem of ARM64 init_cache_level() invoking ACPI
functions which take a semaphore in that context. That's invalid as SMP
function calls run with interrupts disabled. Running it just from the
callback in context of the CPU hotplug thread solves this.
Fixes: 8571890e15 ("arm64: Add support for ACPI based firmware tables")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Will Deacon <will@kernel.org>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/871r69ersb.ffs@tglx
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* MIPS cacheinfo support
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*/
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#include <linux/cacheinfo.h>
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/* Populates leaf and increments to next leaf */
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#define populate_cache(cache, leaf, c_level, c_type) \
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do { \
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leaf->type = c_type; \
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leaf->level = c_level; \
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leaf->coherency_line_size = c->cache.linesz; \
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leaf->number_of_sets = c->cache.sets; \
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leaf->ways_of_associativity = c->cache.ways; \
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leaf->size = c->cache.linesz * c->cache.sets * \
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c->cache.ways; \
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leaf++; \
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} while (0)
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int init_cache_level(unsigned int cpu)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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int levels = 0, leaves = 0;
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/*
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* If Dcache is not set, we assume the cache structures
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* are not properly initialized.
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*/
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if (c->dcache.waysize)
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levels += 1;
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else
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return -ENOENT;
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leaves += (c->icache.waysize) ? 2 : 1;
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if (c->vcache.waysize) {
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levels++;
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leaves++;
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}
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if (c->scache.waysize) {
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levels++;
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leaves++;
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}
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if (c->tcache.waysize) {
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levels++;
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leaves++;
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}
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this_cpu_ci->num_levels = levels;
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this_cpu_ci->num_leaves = leaves;
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return 0;
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}
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static void fill_cpumask_siblings(int cpu, cpumask_t *cpu_map)
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{
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int cpu1;
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for_each_possible_cpu(cpu1)
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if (cpus_are_siblings(cpu, cpu1))
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cpumask_set_cpu(cpu1, cpu_map);
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}
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static void fill_cpumask_cluster(int cpu, cpumask_t *cpu_map)
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{
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int cpu1;
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int cluster = cpu_cluster(&cpu_data[cpu]);
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for_each_possible_cpu(cpu1)
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if (cpu_cluster(&cpu_data[cpu1]) == cluster)
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cpumask_set_cpu(cpu1, cpu_map);
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}
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int populate_cache_leaves(unsigned int cpu)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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struct cacheinfo *this_leaf = this_cpu_ci->info_list;
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int level = 1;
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if (c->icache.waysize) {
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/* I/D caches are per core */
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fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
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populate_cache(dcache, this_leaf, level, CACHE_TYPE_DATA);
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fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
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populate_cache(icache, this_leaf, level, CACHE_TYPE_INST);
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level++;
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} else {
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populate_cache(dcache, this_leaf, level, CACHE_TYPE_UNIFIED);
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level++;
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}
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if (c->vcache.waysize) {
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/* Vcache is per core as well */
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fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
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populate_cache(vcache, this_leaf, level, CACHE_TYPE_UNIFIED);
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level++;
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}
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if (c->scache.waysize) {
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/* Scache is per cluster */
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fill_cpumask_cluster(cpu, &this_leaf->shared_cpu_map);
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populate_cache(scache, this_leaf, level, CACHE_TYPE_UNIFIED);
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level++;
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}
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if (c->tcache.waysize)
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populate_cache(tcache, this_leaf, level, CACHE_TYPE_UNIFIED);
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this_cpu_ci->cpu_map_populated = true;
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return 0;
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}
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