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f0fe60cae6
Add clocks, resets and power domains for USB modules available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
352 lines
14 KiB
C
352 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G3S CPG driver
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*
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* Copyright (C) 2023 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/r9a08g045-cpg.h>
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#include "rzg2l-cpg.h"
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/* RZ/G3S Specific registers. */
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#define G3S_CPG_PL2_DDIV (0x204)
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#define G3S_CPG_SDHI_DDIV (0x218)
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#define G3S_CPG_PLL_DSEL (0x240)
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#define G3S_CPG_SDHI_DSEL (0x244)
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#define G3S_CLKDIVSTATUS (0x280)
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#define G3S_CLKSELSTATUS (0x284)
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/* RZ/G3S Specific division configuration. */
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#define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3)
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#define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1)
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#define G3S_DIV_SDHI1 DDIV_PACK(G3S_CPG_SDHI_DDIV, 4, 1)
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#define G3S_DIV_SDHI2 DDIV_PACK(G3S_CPG_SDHI_DDIV, 8, 1)
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/* RZ/G3S Clock status configuration. */
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#define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1)
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#define G3S_DIVPL2B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 5, 1)
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#define G3S_DIVPL3A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 8, 1)
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#define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1)
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#define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1)
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#define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1)
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#define G3S_DIV_SDHI1_STS DDIV_PACK(G3S_CLKDIVSTATUS, 25, 1)
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#define G3S_DIV_SDHI2_STS DDIV_PACK(G3S_CLKDIVSTATUS, 26, 1)
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#define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1)
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#define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1)
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#define G3S_SEL_SDHI1_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 17, 1)
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#define G3S_SEL_SDHI2_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 18, 1)
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/* RZ/G3S Specific clocks select. */
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#define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1)
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#define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2)
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#define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2)
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#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)
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/* PLL 1/4/6 configuration registers macro. */
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#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12)
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#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
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DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
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.parent_names = (_parent_names), \
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.num_parents = ARRAY_SIZE((_parent_names)), \
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.mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
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.flag = (_clk_flags))
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A08G045_SWD,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_OSC_DIV1000,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_DIV2,
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CLK_PLL2_DIV2_8,
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CLK_PLL2_DIV6,
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL3_DIV2_4,
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CLK_PLL3_DIV2_8,
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CLK_PLL3_DIV6,
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CLK_PLL4,
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CLK_PLL6,
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CLK_PLL6_DIV2,
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CLK_SEL_SDHI0,
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CLK_SEL_SDHI1,
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CLK_SEL_SDHI2,
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CLK_SEL_PLL4,
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CLK_P1_DIV2,
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CLK_P3_DIV2,
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CLK_SD0_DIV4,
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CLK_SD1_DIV4,
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CLK_SD2_DIV4,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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/* Divider tables */
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static const struct clk_div_table dtable_1_2[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_1_8[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 2, 4 },
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{ 3, 8 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_1_32[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 2, 4 },
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{ 3, 8 },
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{ 4, 32 },
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{ 0, 0 },
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};
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/* Mux clock names tables. */
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static const char * const sel_sdhi[] = { ".pll2_div2", ".pll6", ".pll2_div6" };
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static const char * const sel_pll4[] = { ".osc_div1000", ".pll4" };
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/* Mux clock indices tables. */
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static const u32 mtable_sd[] = { 0, 2, 3 };
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static const u32 mtable_pll4[] = { 0, 1 };
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static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3),
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DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
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DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
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DEF_FIXED(".pll3_div2_8", CLK_PLL3_DIV2_8, CLK_PLL3_DIV2, 1, 8),
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DEF_FIXED(".pll3_div6", CLK_PLL3_DIV6, CLK_PLL3, 1, 6),
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DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2),
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DEF_SD_MUX(".sel_sd0", CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi,
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mtable_sd, 0, NULL),
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DEF_SD_MUX(".sel_sd1", CLK_SEL_SDHI1, G3S_SEL_SDHI1, G3S_SEL_SDHI1_STS, sel_sdhi,
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mtable_sd, 0, NULL),
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DEF_SD_MUX(".sel_sd2", CLK_SEL_SDHI2, G3S_SEL_SDHI2, G3S_SEL_SDHI2_STS, sel_sdhi,
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mtable_sd, 0, NULL),
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DEF_SD_MUX(".sel_pll4", CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4,
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mtable_pll4, CLK_SET_PARENT_GATE, NULL),
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/* Core output clk */
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DEF_G3S_DIV("I", R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8,
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0, 0, 0, NULL),
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DEF_G3S_DIV("P0", R9A08G045_CLK_P0, CLK_PLL2_DIV2_8, G3S_DIVPL2B, G3S_DIVPL2B_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_G3S_DIV("SD0", R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS,
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dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT,
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rzg3s_cpg_div_clk_notifier),
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DEF_G3S_DIV("SD1", R9A08G045_CLK_SD1, CLK_SEL_SDHI1, G3S_DIV_SDHI1, G3S_DIV_SDHI1_STS,
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dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT,
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rzg3s_cpg_div_clk_notifier),
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DEF_G3S_DIV("SD2", R9A08G045_CLK_SD2, CLK_SEL_SDHI2, G3S_DIV_SDHI2, G3S_DIV_SDHI2_STS,
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dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT,
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rzg3s_cpg_div_clk_notifier),
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DEF_FIXED(".sd0_div4", CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4),
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DEF_FIXED(".sd1_div4", CLK_SD1_DIV4, R9A08G045_CLK_SD1, 1, 4),
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DEF_FIXED(".sd2_div4", CLK_SD2_DIV4, R9A08G045_CLK_SD2, 1, 4),
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DEF_FIXED("M0", R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
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DEF_G3S_DIV("P1", R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A08G045_CLK_P1, 1, 2),
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DEF_G3S_DIV("P2", R9A08G045_CLK_P2, CLK_PLL3_DIV2_8, DIVPL3B, G3S_DIVPL3B_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2),
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DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1),
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DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2),
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DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1),
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DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3),
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DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2),
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};
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static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
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DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0),
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DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
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DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
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DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
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DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1),
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DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0),
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DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1),
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DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
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DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1),
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DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2),
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DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3),
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DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4),
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DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5),
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DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6),
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DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7),
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DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8),
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DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9),
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DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10),
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DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11),
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DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0),
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DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1),
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DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2),
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DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3),
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DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0),
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DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0),
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DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8),
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DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
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DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
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DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
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DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),
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DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),
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DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
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DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
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DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
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DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
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DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
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};
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static const struct rzg2l_reset r9a08g045_resets[] = {
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DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
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DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
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DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
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DEF_RST(R9A08G045_DMAC_ARESETN, 0x82c, 0),
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DEF_RST(R9A08G045_DMAC_RST_ASYNC, 0x82c, 1),
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DEF_RST(R9A08G045_WDT0_PRESETN, 0x848, 0),
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DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
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DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
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DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
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DEF_RST(R9A08G045_USB_U2H0_HRESETN, 0x878, 0),
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DEF_RST(R9A08G045_USB_U2H1_HRESETN, 0x878, 1),
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DEF_RST(R9A08G045_USB_U2P_EXL_SYSRST, 0x878, 2),
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DEF_RST(R9A08G045_USB_PRESETN, 0x878, 3),
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DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
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DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
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DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
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DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1),
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DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
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DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
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DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
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DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
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DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
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DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
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DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
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};
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static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
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MOD_CLK_BASE + R9A08G045_GIC600_GICCLK,
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MOD_CLK_BASE + R9A08G045_IA55_PCLK,
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MOD_CLK_BASE + R9A08G045_IA55_CLK,
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MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
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MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
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};
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static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
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/* Keep always-on domain on the first position for proper domains registration. */
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DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
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DEF_REG_CONF(0, 0),
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RZG2L_PD_F_ALWAYS_ON),
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DEF_PD("gic", R9A08G045_PD_GIC,
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DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
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RZG2L_PD_F_ALWAYS_ON),
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DEF_PD("ia55", R9A08G045_PD_IA55,
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DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
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RZG2L_PD_F_ALWAYS_ON),
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DEF_PD("dmac", R9A08G045_PD_DMAC,
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DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
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RZG2L_PD_F_ALWAYS_ON),
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DEF_PD("wdt0", R9A08G045_PD_WDT0,
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DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
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RZG2L_PD_F_NONE),
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DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
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RZG2L_PD_F_NONE),
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DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
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RZG2L_PD_F_NONE),
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DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
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RZG2L_PD_F_NONE),
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DEF_PD("usb0", R9A08G045_PD_USB0,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, GENMASK(6, 5)),
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RZG2L_PD_F_NONE),
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DEF_PD("usb1", R9A08G045_PD_USB1,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(7)),
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RZG2L_PD_F_NONE),
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DEF_PD("usb-phy", R9A08G045_PD_USB_PHY,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(4)),
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RZG2L_PD_F_NONE),
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DEF_PD("eth0", R9A08G045_PD_ETHER0,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
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RZG2L_PD_F_NONE),
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DEF_PD("eth1", R9A08G045_PD_ETHER1,
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DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
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RZG2L_PD_F_NONE),
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DEF_PD("i2c0", R9A08G045_PD_I2C0,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),
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RZG2L_PD_F_NONE),
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DEF_PD("i2c1", R9A08G045_PD_I2C1,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),
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RZG2L_PD_F_NONE),
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DEF_PD("i2c2", R9A08G045_PD_I2C2,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),
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RZG2L_PD_F_NONE),
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DEF_PD("i2c3", R9A08G045_PD_I2C3,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),
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RZG2L_PD_F_NONE),
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DEF_PD("scif0", R9A08G045_PD_SCIF0,
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DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
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RZG2L_PD_F_NONE),
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DEF_PD("vbat", R9A08G045_PD_VBAT,
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DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
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RZG2L_PD_F_ALWAYS_ON),
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};
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const struct rzg2l_cpg_info r9a08g045_cpg_info = {
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/* Core Clocks */
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.core_clks = r9a08g045_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a08g045_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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|
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/* Critical Module Clocks */
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.crit_mod_clks = r9a08g045_crit_mod_clks,
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.num_crit_mod_clks = ARRAY_SIZE(r9a08g045_crit_mod_clks),
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|
|
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/* Module Clocks */
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.mod_clks = r9a08g045_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks),
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.num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1,
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|
|
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/* Resets */
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.resets = r9a08g045_resets,
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.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
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|
|
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/* Power domains */
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.pm_domains = r9a08g045_pm_domains,
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.num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
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|
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.has_clk_mon_regs = true,
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};
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