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02ab3f7079
This is the second version of the shared interrupt controller patch for the sh architecture, fixing up handling of intc_reg_fns[]. The three main advantages with this controller over the existing ones are: - Both priority (ipr) and bitmap (intc2) registers are supported - External pin sense configuration is supported, ie edge vs level triggered - CPU/Board specific code maps 1:1 with datasheet for easy verification This controller can easily coexist with the current IPR and INTC2 controllers, but the idea is that CPUs/Boards should be moved over to this controller over time so we have a single code base to maintain. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org> |
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| .. | ||
| irq | ||
| sh2 | ||
| sh2a | ||
| sh3 | ||
| sh4 | ||
| sh4a | ||
| adc.c | ||
| clock.c | ||
| init.c | ||
| Makefile | ||
| ubc.S | ||